A
system for performing
decimal floating point addition. The
system includes input registers for inputting a first and second
operand for an addition operation. The
system also includes a plurality of
adder blocks, each calculating a sum of one or more corresponding digits from the first
operand and the second
operand. Output from each of the
adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first
clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of
adder blocks, the storing during the first
clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first
clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.