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Leading zero prediction in floating point addition

A floating-point value and adding circuit technology, which is applied in the direction of instruments, data transformation, electrical digital data processing, etc., can solve problems affecting the performance of adder units, etc.

Active Publication Date: 2012-10-03
ARM LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, another pipeline stage may have to be added to the near path to allow rounding to be performed, and this may significantly affect the performance of the adder unit

Method used

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  • Leading zero prediction in floating point addition
  • Leading zero prediction in floating point addition
  • Leading zero prediction in floating point addition

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0122] LSA, classic far path (example of LSA shifted right forever)

[0123] 1.011e4

[0124] +1.101e2

[0125] Before adding, we need to make the exponents the same, so the smaller number has to be shifted right two places.

[0126]

[0127] refer to figure 2 , in the example above, the output 180 of the LZA would be ignored, the smaller operand would be right shifted using the right shift circuit 200, and the output from the add0 adder 260 would be selected since there was no overflow.

example 2

[0129] USA shifts right, classic far path

[0130] 1.011e4

[0131] -1.001e2

[0132] Before subtracting, we need to make the exponents the same, so the smaller number has to be shifted right two places by the right shift circuit 200 .

[0133]

[0134] Subtraction is done in two complementary arithmetics by inverting the subtrahend and adding to the minuend (minuend - minuend = difference). We also left-shift the subtraction by one position and decrement the exponent so that the exponent works (it's a subtraction, so the exponent can be smaller than what we started with, but it can't be larger). We let add0 handle the case where the exponent gets smaller, and let add1 handle the case where the difference "overflows". refer to figure 2 , in one embodiment, the above can be achieved by adding logic to converter 165 in stage E2 to invert the subtrahend, adding logic to both multiplexers 205, 210 in stage E3 to left shift the two valid and then a 1 value as another input...

example 3

[0140] USA with the same exponent, left shift required, classic short path

[0141] 1.110e4

[0142] -1.100e4

[0143] Converting to two complementary additions, this becomes:

[0144]

[0145] The result is not a normalized number (a normalized floating-point number should be in the form of 1.xxx multiplied by an exponent). So what we do is use the LZA output 180 to tell us how much to left shift both operands, and then use the left shift circuits 190, 195 to perform the required left shift. In this case, the predicted LZA is 3, so the addition becomes:

[0146]

[0147] The carry-out means that the correct answer comes from the overflow adder 250, which has an exponent higher than one, ie:

[0148] 1.000e2

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PUM

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Abstract

An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent. The apparatus comprises prediction circuitry for generating a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition. Further, result pre-normalization circuitry performs a shift operation on the significands of both operand A and operand B prior to addition of the significands, this serving to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for operands A and B. Operand analysis circuitry detects, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition, and addition circuitry is configured, in the presence of the leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R. Such an approach provides a particularly simple and efficient apparatus for performing addition operations.

Description

technical field [0001] The present invention relates to apparatus and methods for performing an addition operation on operands A and B to produce a result R which is a floating point value each having a significand and an exponent . Background technique [0002] Floating point numbers can be represented as follows: [0003] ±1.x*2 y [0004] where: x = score [0005] 1. x = significant number (also called mantissa) [0006] y = index [0007] Floating-point addition can take two forms, ie, like-signed addition (LSA, like-signed addition) or like-signed addition (USA, unlike-signed addition). If two floating-point operands with the same sign are to be added, or, if two floating-point operands with different signs are to be subtracted, an LSA operation is performed. Similarly, if two floating-point operands with different signs are to be added, or if two floating-point operands with the same sign are to be subtracted, the USA operation is performed. When reference is m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
CPCG06F7/485G06F7/57G06F7/76G06F5/012G06F7/5443G06F7/74
Inventor 大卫·雷蒙德·鲁茨
Owner ARM LTD
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