127 results about "Bit manipulation" patented technology

An efficient method of generating a bit-reverse index array in real time without performing any bit manipulation for a wireless communication system.

Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations.

A processor generates a mode indication based on two or more other indications. The mode indication is indicative of whether or not a particular mode is active in the processor. Each indication is stored in a storage location which is addressable via a different instruction. In one embodiment, a long mode in which a 64 bit operating mode is selectable in addition to 32 bit and 16 bit modes may be activated via a long mode active indication. The long mode active indication may be generated by the processor, and may indicate that long mode is active if paging is enabled and a long mode enable indication indicates that long mode is enabled. In this manner, long mode may be activated after paging is enabled (with a set of long mode page tables indicated by the page table base address).

The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing.

A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code "cc" that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant "const". The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing. The present invention further provides an interconnection scheme so that a plurality of ACE devices operates under the control of a single k-node.

Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.

A bit field direct manipulation device which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Circuitry (fixed or configured in a programmable device) for performing floating point addition and subtraction uses approximately the same resources as required for either operation separately. The circuitry is based on a recognition that when adding or subtracting two numbers, the two resulting mantissa values will be two out of three possibilities, and will involve either a one-bit shifting operation, or a shifting operation involving a large number of bits. Therefore, one mantissa path—a subtraction path—can be provided with full add/normalize/round circuitry, while a second mantissa path—an addition path—can be provided with a simple one-bit shifter and simplified rounding circuitry. Because the input numbers are signed, the “addition path,” which only adds the mantissas, may provide the mantissa for the subtraction result, depending on the signs of the input numbers. Similarly, the “subtraction path” may provide the mantissa for the addition result.

A thermometer code converter for converting weightless binary tuples of 2 or higher dimensional arrays into a thermometer or aggregate code comprises a series of layers (16, 18) each made up of bit manipulation cells (10) which collectively cause set bits to be shifted towards a required bit position. The bit manipulation cells are made up of logic elements (12, 14) and the entire converter may be asynchronous. Also disclosed is a sum and threshold device which employs a thermometer code converter and a bit selector device.

The invention relates to a method for controlling different products by using a same rule and aims at solving the deficiency in the prior art. The method comprises the following steps: I, firstly generating a pattern file of a conversion rule and analyzing a communication protocol of target hardware which is defined by adopting C language; II, describing structure information of the C language in the communication protocol of the target hardware by using an xml file; III, converting the structure information described by the xml into description information; IV, setting a conversion rule of json according to the step III so as to form a binary description file; V, converting a function rule of the target hardware through an lua script and carrying out conversion supplementation on bit manipulation content in the communication protocol of the target hardware through the lua script at the same time so as to form a character string in a json format; VI, converting the character string in the json format into binary data of the C language through the pattern file; and VII, executing corresponding functions by the target hardware according to the binary data of the C language.

The comparators described herein comprise bit manipulation cells of a number of logic cells each built up of AND, OR etc. logic gates interconnected in parallel to make up one or more layers and do not rely on clocks, instead operating asynchronously. This makes the comparators highly robust and fault tolerant, and well suited for use as binary neurons in high integrity systems. They are less susceptible to radio frequency interference induced data corruption than alternative register-based implementations. Planar Hamming comparators capable of comparing two dimensional input arrays are also described.

The invention provides an image compression method and device based on run-length encoding (RLE). The image compression method includes that whether pixel values of adjacent pixels in an image to be compressed are identical is sequentially compared and judged, the zone bit in the pixel format is set to be the value adopting RLE and RLE is performed on yes judgment, otherwise the zone bit is set to be the value not adopting RLE and RLE is not performed; during decoding, whether RLE is adopted is judged according to the zone bit in the pixel format of a pixel to be decoded, and RLE is adopted on yes judgment; and the zone bit is the bit with the smallest color display influence caused by G in the red, green and blue (RGB) pixel format. The image compression method and device can solve the problem of the traditional RLE algorithm of data quantity increasing after coding on some conditions, reach a compression ratio larger than that of the RLE algorithm only by losing little pixel accuracy, and are simple and convenient due to the fact that only shifting and bit manipulation are adopted in the whole encoding and decoding processes.

Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation. Multiple data shift commands may be utilized such that the plurality of code blocks have an individual shifting command to thereby implement different data shifting with respect to each code block.

The invention relates to image decomposition strategies and computer-based methods for implementing them. In one method of the invention, the ordering of tetrahedral shapes that define or approximate an image is performed in such a way that neighboring tetrahedral shapes can be identified, located and efficiently used. In one aspect, a binary location code array is used to represent an image and the method for identifying the neighbor shape employs a bit manipulation step in code or pseudo-code for operating a computer. In this aspect, the invention allows one to move between adjacent tetrahedra, and any data corresponding to the tetrahedra, in constant time.

An inventive method for multi-symbol polarization switching for differential detection optical systems includes modulating a laser source by a DQPSK modulator, driving the DQPSK modulator with a data block configured for generating multi-symbol polarization-switched DQPSK differential-encoded signals, and polarizing the multi-symbol polarization-switched DQPSK signals with a polarizing modulator whose modulation speed is based on how often polarization states vary, wherein the data block provides a bits manipulation to provide the multi-symbol polarization switching thereby enabling differential detection for recovering correct original data by a receiver.

A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift indication based on a prediction of the number of bit positions by which the data value needs to be shifted in order to normalize the data value. Further, normalizer logic is used to apply a shift operation to the data value based on the shift indication. In addition, correction logic is operable in parallel with the normalizer logic to determine from the data value and a least significant bit of the shift indication whether the shift indication has correctly predicted the number of bit positions by which the data value needs to be shifted in order to normalize the data value, or whether instead the prediction is incorrect, and to generate an output signal dependent on that determination. Shift logic is then used, if the output signal indicates that the prediction is incorrect, to apply a correction shift such that the result value is the normalized data value.

The invention discloses a colorful commodity anti-counterfeiting code generating method. The colorful commodity anti-counterfeiting code generating method comprises the following steps: converting a commodity identification code for representing the unique identity information of a certain commodity into a binary data; obtaining an initial value and parameters of a chaotic system based on the commodity identity information and an external secret key through calculation, and performing iteration on a chaotic mapping to generate two groups of chaotic signal binary sequences; performing bit manipulation taking 2bits as a unit on the commodity identification code by the chaotic binary signals to generate an anti-counterfeiting number overlapped with a colorful background, and further combining the anti-counterfeiting number into the colorful commodity anti-counterfeiting code. The colorful commodity anti-counterfeiting code generating method provided by the invention is simple, feasible, high in safety, and difficult to be cracked; and in addition, the generated colorful commodity anti-counterfeiting code is has the uniqueness and unforgeability.

An integrated circuit device comprising at least one instruction processing module arranged to receive a bit-manipulation instruction, and in response to receiving the bit-manipulation instruction to select at least one bit from at least one source data register in accordance with a value of at least one control bit, select from candidate values a manipulation value for the at least one selected bit in accordance with a value of at least one further control bit, and store the selected manipulation value for the at least one selected bit in at least one output data register.

An extremely fast data encryption, decryption and secure hash scheme encrypts or hashes data of any size, and can be implemented in a variety of software or hardware based data processing devices. A key and data are prepared for processing by separating them into a series of four byte integers, pad with zero bytes as necessary. A bit manipulation unit having four registers A, B, C and D that are each thirty-two bits long is initialized by loading the key into the registers. A series of operations are performed on the registers to manipulate bits in the registers. An exclusive OR (XOR) operation is then performed on contents of register D and a portion of the data to be processed.