146 results about "Bit manipulation" patented technology

The invention provides a bit slice accelerator for efficient convolutional neural network reasoning, and belongs to the field of neural network reasoning hardware. The bit slice accelerator comprises a lookup table (LUT)-based multiplier which comprises a bit operation analysis unit (BMAU) and a bit level multiplier unit; and the BMAU manages bit-level multiplication operation by utilizing an LUT mechanism and performs bit field division on input data, and the bit-level multiplier unit processes groups of continuous multiplier bits after bit field division so as to realize bit-level data processing. According to the bit slice accelerator provided by the invention, through the multiplier based on the lookup table LUT, the BMAU of the integrated bit level and the bit level multiplier unit are included, and operation of different bit widths is supported; data sparsity can be effectively utilized in DNN reasoning, and reasoning efficiency and energy efficiency in a limited environment are remarkably improved.

The embodiment of the invention relates to the field of data processing, and discloses a floating-point number operation method and device. According to the method, a difference absolute value of order digits of two floating-point numbers is utilized to perform order alignment on a small mantissa, and a mantissa operation type system signal and a final calculation result sign bit are obtained through sign bit processing operation; if the mantissa operation type system signal indicates to perform negation operation, performing unsigned fixed-point full addition operation by using the large mantissa and the small mantissa subjected to negation operation; performing normalization shift operation on the result of the unsigned fixed-point full addition operation through the leading zero number and the shift remainder of the result of the unsigned fixed-point full addition operation, and performing overflow judgment and result normalization processing on the normalization result by utilizing an index adjustment result and a final calculation result sign bit. In this way, most of the operation logic of original code and complement conversion is omitted, the calculation precision is guaranteed, meanwhile, the scale of a logic circuit is reduced, and the calculation power density is improved.

The invention discloses a resource allocation method and device based on bit map pre-calculation, and the method comprises the steps: generating a global resource state bitmap according to the CORESET configuration in a PDCCH, and carrying out the pre-calculation of each possible candidate PDCCH to form a candidate pre-allocation bit map set; extracting a corresponding pre-allocation bitmap from the candidate pre-allocation bitmap set as a candidate set bitmap; and comparing the candidate set bitmap with the global resource state bitmap, judging whether the resources are conflicted or not, and if the resources are not conflicted, determining that the resources are available and further occupying the resources. Complex function calculation at the scheduling moment is transferred to pre-calculation at the initialization stage, only simple bitmap retrieval and bit operation are needed during scheduling, the PDCCH resource allocation time consumption is greatly shortened, real-time intensive calculation is replaced with pre-stored bitmaps, the CPU load is remarkably reduced, a processor focuses on a core scheduling algorithm, resource redundancy consumption is reduced, and the scheduling efficiency is improved. And the overall capacity and the energy utilization efficiency of the communication system are effectively improved.

The invention provides an ML-DSA module reduction method and device based on improved Barrett reduction, and the method comprises the steps: dividing an input signal into a first preset bit signal and a second preset bit signal according to the bit width, and carrying out the shift addition operation of the first preset bit signal, so as to generate a middle quotient value; generating a first preset bit remainder based on the intermediate value; performing splicing processing on the first preset bit remainder and the second preset bit signal to generate an intermediate remainder; and performing a correction operation on the intermediate remainder to output a remainder result. According to the operation method, an input signal is processed in a high-order mode and a low-order mode, and the bit width participating in multiplication and shifting operation is reduced; according to the method, a precomputation constant is optimized, the number of times of addition is reduced, and wide bit operation in a critical path is eliminated by means of segmentation processing and register insertion, so that the critical path is shortened, and the maximum operation frequency of a system clock is improved; and through error analysis and range limitation, the correctness of a module reduction result is ensured.

The invention relates to the technical field of passwords, in particular to an Ascon algorithm optimization implementation method based on an RISC-V processor, and the method comprises the steps: reconstructing S-box substitution logic through RISC-V assembly; 64-bit cyclic shift is optimized through a bit interleaving technology; fully expanding assembly codes to eliminate cycle overhead; the intermediate state and the key are stored in a register. According to the method, the execution efficiency and performance of the Ascon algorithm on an RISC-V platform are remarkably improved through multiple technical means, redundant bit operation is effectively reduced through reconstruction of S-box substitution logic, calculation delay is reduced through optimization of bit operation sequences and multiplexing of temporary variables, 64-bit cyclic shift operation is decomposed through the bit interleaving technology, and the calculation efficiency of the algorithm is improved. The operation is more efficient, the overhead of loop control is eliminated through an assembly-level full-expansion technology, unnecessary jump instructions are avoided, the execution speed is further improved, and the problems of insufficient Ascon algorithm performance and resource waste caused by low utilization rate of the RISC-V architecture are effectively solved.

The embodiment of the invention provides a data processing method based on an ARM (Advanced RISC Machines) instruction set, which comprises the following steps of: generating an index sequence corresponding to to-be-shifted data in response to a shifting instruction carrying a shifting parameter, and then realizing shifting operation on the to-be-shifted data by using the index sequence to be matched with a TBL (Tunnel Bit Language) instruction. According to the method, the shift operation of the to-be-shifted data with different lengths can be realized by adjusting the total number of the data indexes and the invalid indexes in the index sequence, and the shift operation is not limited by the length of the to-be-shifted data, for example, when 16-bit indexes (including the data indexes and the invalid indexes) exist in the index sequence, the shift operation is not limited by the length of the to-be-shifted data; according to the data processing method, the displacement operation of the 128 (16 * 8)-bit data to be displaced can be realized by matching with the TBL instruction, the limitation that the displacement instruction in the traditional ARM instruction set can only realize the displacement operation of the 64-bit or less-length data to be displaced is broken through, and the purposes of improving the adaptability of the data processing method and meeting the multi-scene data displacement requirement are realized.

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.

The invention discloses a low-delay Montgomery modular multiplier. The modular multiplier comprises an iteration control unit, a parallel part and generation unit, a quotient operation unit of a multi-stage pipeline, an output shifting unit, a part and compression unit and a final reduction unit. According to the modular multiplier, an intermediate result of each round of iteration is expressed in a triple form, and the number of compression stages is reduced while long-bit-width addition is avoided. According to the method, shift operation is introduced, the quotient operation process is dispersed to a plurality of cycles for pipeline implementation, at the cost of introducing a plurality of additional cycles, the key path of each round of iteration is greatly shortened, the overall output delay of the modular multiplier is greatly reduced, the method is suitable for scenes with high-speed operation requirements, and the longer the modulus length is, the more obvious the acceleration effect is.

The invention relates to the technical field of solid-state storage, and discloses an end-to-end data path protection method and system for a high-capacity solid-state hard disk, and the method comprises the steps: carrying out the real-time lightweight feature extraction of a data block; generating a dynamic feature matrix from the feature vectors, performing bit operation between the data blocks and the dynamic feature matrix, and performing LDPC coding on an intermediate data matrix; constructing mapping table entries for protecting the data blocks in the high-capacity solid state disk, and performing feature matrix nesting protection on the mapping table entries; and writing the protection data block and the protection mapping table item into the high-capacity solid state disk, and reading the protection data block and the protection mapping table item from the high-capacity solid state disk. According to the method, the dynamic matrix can be generated by fusing the data entropy value, the key mode and the physical state in real time, ECC strength self-adaption is achieved, user data features are embedded into a mapping table item, the same protection process is reused, a bidirectional verification chain is constructed, a feature matrix is bound from an NAND physical layer to a host interface in a full-link mode, and protection breakpoints are eliminated.

A data aggregation service is engineered to generate aggregated data values based on encrypted data received from a variety of providers, without being exposed to the underlying plaintext data. A homomorphic encryption scheme is used in a threshold cryptography scenario that allows aggregation of the encrypted data without requiring decryption. An independent decryption service can partially decrypt the aggregated result, which can ultimately be decrypted to plaintext for use by the provider. Bitwise operations can be defined to support aggregation with error tolerance, and the operations can be constrained to a smaller bit size to reduce circuit complexity.

To automatically test an OS incorporated in equipment or a control board.SOLUTION: An acquisition unit 51 that communicates with a repository via a network and acquires a source code of a target program from the repository, a build unit 52 that builds the target program using the acquired source code, a writing unit 53 that performs a process of writing the built target program to a storage unit of a target board, a reset unit 54 that performs a process of resetting the target board, a communication unit 55 that communicates with the target board, instructs a control unit of the target board to execute an automatic test, and receives a test result of the automatic test from the target board, and a determination unit 56 that performs a process of determining results of various tests executed on the target board based on the received test result.SELECTED DRAWING: Figure 6

Provided are a method and an apparatus for enhancing the security of a quantum key distribution network. The quantum key distribution network includes a first node, a second node, and at least one relay node, by means of which the first node and the second node implement a first stage of quantum key distribution; the first node and the second node share a first key pool, which includes at least one key; and the method is executed on either the first node or the second node. The method includes: acquiring a first key obtained after the first stage of quantum key distribution; determining the seed key from the first key pool; generating a first random string by applying, based on the seed key, a first algorithm predetermined with a correspondent node, the first random string having a length equal to that of the first key; and acquiring a second key by performing a preset first bit operation on the first key and the first random string.

The invention relates to an implementation method for applying linear subcomponents of a ZUC algorithm to multiple scenes. The method comprises the following steps: constructing a linear transformation matrix expression from an input bit sequence to an output bit sequence of a linear subcomponent according to the definition of the linear subcomponent in the ZUC algorithm; and carrying out structure division on the linear transformation matrix expression, and decomposing the original large-scale matrix operation into at least two independent small-scale matrix operations. And according to each small-scale matrix design, a logic gate level implementation scheme based on in-situ XOR operation is designed, and a bit operation sequence is generated. And mapping the logic gate-level implementation scheme into a plurality of physical circuit modules with a hierarchical connection relationship according to the data dependency relationship among the bit operation sequences, so that all the physical circuit modules jointly form a component structure suitable for multiple scenes. By adopting the method, the reliability and applicability of the communication system or equipment for executing the ZUC algorithm can be enhanced.

The invention discloses a storage and calculation integrated hardware accelerator and system based on high-density cache. In the accelerator, a storage unit array comprises a plurality of 2T eDRAM units, and a read word line decoder is used for selecting storage units storing operands to be operated from the storage unit array; the induction amplifier is used for reading an operand to be operated of the storage unit array as a digital signal according to a set reference voltage to obtain a corresponding logical operation result; the shifter is used for performing shifting operation on the logic operation result output by the induction amplifier as required; and the write bit line driving module is used for selecting an operation result from the output end of the induction amplifier or the output end of the shifter and storing the operation result to a corresponding storage unit of the storage unit array through write-back operation. According to the accelerator designed by the invention, an analog-to-digital converter is not needed, relatively high storage density can be achieved, large-scale logic parallel operation can be realized, addition and multiplication can also be realized, and an application scene is expanded.

The invention discloses a low-disturbance self-recovery operation method for a cross-point array ferroelectric memory, which is used for operating a cross-point array ferroelectric memory array, comprises four continuous pulse periods, and sequentially realizes selected memory unit activation, data reading, data recovery and reset operation. By using the low-disturbance self-recovery operation method provided by the invention, the voltage pulse disturbance suffered by unselected units in the operation process of the cross-point array ferroelectric capacitance memory can be reduced, and meanwhile, the function of automatically recovering the data of the ferroelectric capacitance memory is realized. According to the method, smaller read-write disturbance can be realized, the bit error rate is lower, and the access speed is higher.

A calculator for calculating a plurality of square roots includes a memory array, at least two registers, a bit subtractor, and a controller. The memory array is organized into columns and rows. The registers store a fixed value. The controller, operatively coupled to the other components, allocates a first set of rows to test variables and a second set to result variables, and initially stores each of a plurality of radicands in a separate column. For multiple iterations, the controller concurrently activates selections of rows to form current operands and current guesses for each column. The controller then instructs the bit subtractor to perform subtraction operations. For each column with a positive subtraction result, the controller selectively writes a new bit of the square root and selectively overwrites values with a new remainder derived from the subtraction result, without performing an explicit data-shifting operation.

The present invention provides a bit-slicing accelerator for efficient convolutional neural network reasoning, belonging to the field of neural network reasoning hardware. The bit-slicing accelerator includes a multiplier based on a lookup table LUT, which includes a bit operation analysis unit BMAU and a bit-level multiplier unit; the BMAU uses the LUT mechanism to manage the bit-level multiplication operation, divides the input data into bit segments, and the bit-level multiplier unit processes the grouping of continuous multiplier bits after the bit segment division to realize bit-level data processing. The bit-slicing accelerator provided by the present invention supports operations of different bit widths through a multiplier based on a lookup table LUT, including an integrated bit-level BMAU and a bit-level multiplier unit; it can effectively utilize data sparsity in DNN reasoning, and significantly improve the reasoning efficiency and energy efficiency in a restricted environment.

A system and methods for determining compression performance of codebooks in resource-constrained computing environments using only integer operations. The system enables accurate prediction of compression performance without codebook generation on devices lacking floating-point units by utilizing bit manipulation techniques. Sourceblock occurrences are tracked using integer counters, with sum of squared probabilities calculated through integer multiplication. Logarithmic approximations are performed using most significant bit position analysis and bit-shifts replace division operations when sourceblock lengths are constrained to powers of 2. This approach requires minimal memory resources, just four integer registers beyond occurrence counters, making compression optimization viable on ultra-low-power 32-bit microcontrollers with less than 64 KB memory, such as those used in wearables and IoT devices, while maintaining accuracy within one bit of theoretical optimal performance.

The invention relates to a DAC digital calibration circuit and an implementation method thereof, and the circuit comprises a multiplier which is used for receiving DAC original conversion data and a slope calibration parameter for multiplication operation, and outputting a result bit width which comprises a DAC bit width and a calibration parameter bit width; the shift register is used for performing shift operation on the result output by the multiplier to obtain a decimal multiplication result to complete slope calibration; the adder is used for adding the decimal multiplication result output by the shift register with the zero calibration parameter and trimming the zero error; the selector is used for receiving an output result of the adder; if the high-order data is not 0, full-scale data of all 1 codes are selected to be output; otherwise, selecting the summator to output the result; and the data register is used for registering the result output by the selector. According to the invention, actual measurement analysis is carried out on the chip behind the flow sheet, then calibration and trimming parameters are determined, inherent errors of the chip are compensated, and higher precision is realized.

The embodiment of the invention provides a data transmission method, a shifter and an FPGA chip. The method comprises the following steps: setting a shift pointer; obtaining a valid data start pointer; according to the shift pointer and the valid data start pointer, shift operation information is determined, and the shift operation information is used for indicating a left shift number; performing a shift operation according to the shift operation information; updating the effective data length of the downstream module; under the condition that the effective data length of the downstream module is larger than or equal to the bit width of the downstream module, a target signal is generated, and the target signal is used for indicating the downstream module to take away data; after the downstream module takes away the data, the shift pointer is updated, and the valid data start pointer is updated. According to the technical scheme provided by the embodiment of the invention, under the condition that the effective data length of the downstream module is greater than or equal to the bit width of the downstream module, the downstream module is notified to take away the data in time, so that bit width adaptation is completed, an additional bit width adaptation module does not need to be arranged, and the logic resource consumption is reduced.

The invention discloses a binary MDS array code structure with high erasure correction performance and a decoding method, and the decoding method achieves the rapid calculation of a syndrome vector through an optimized scheduling algorithm, only needs the exclusive or and cyclic shift operation, reduces the calculation complexity to a linear level O (n), and remarkably improves the data recovery speed. Compared with a traditional RS code and an existing array code, high reliability is guaranteed, the technical problem that storage efficiency and calculation complexity are difficult to consider at the same time is solved, and the method is suitable for large-scale distributed storage scenes such as cloud computing and artificial intelligence training. According to the binary MDS array code structure with the high erasure performance and the decoding method, the fault-tolerant capability is improved to five-node failure, and the high-reliability storage requirement is met; the decoding calculation complexity is obviously reduced, and only xor and shift operations are needed; the storage efficiency reaches the upper bound of the MDS theory, and the storage cost is reduced; and efficient data recovery is realized under the configuration that the code length n is equal to 11 and the redundancy r is equal to 5.

A system and method for hardware-accelerated determination of hybrid codebook performance using FPGA implementation. The system transforms the mathematical operations of estimating combined performance of primary and secondary codebooks into dedicated hardware circuits on field-programmable gate arrays. By implementing specialized components for primary term calculation, secondary term calculation, and mismatch probability estimation directly in hardware, the system enables wire-speed performance estimation without generating test codebooks. The FPGA design comprises parallel processing paths, dedicated bit manipulation circuits for logarithmic approximation, and specialized memory structures for occurrence tracking. This hardware implementation enables real-time hybrid codebook optimization in high-throughput environments such as network appliances, storage controllers, and data processing systems, while providing a development pathway toward eventual ASIC implementation for mass-market deployment.

A method and apparatus for reducing computation time are disclosed herein which provides in at least one embodiment a computer-implemented method for reducing computation time, the computer-implemented method including the steps of: receiving one or more bits from a multiplier, generating a shift signal by using the one or more bits, performing a shift operation by n bits (where n is a natural number) based on the shift signal to obtain a partial product, and generating an output product by using the partial product and then outputting the output product.

The embodiment of the invention provides a quantum computing measurement and control system and a quantum computer, and relates to the technical field of quantum computing, and the system comprises a central control board card, a routing board card and a functional board card; the central control board card is connected with the routing board card through a plurality of first channels based on an LVDS protocol; the central control board card is used for decomposing the trigger signal into a first sub-signal; sending to a routing board card through each first channel; the routing board card is used for receiving each first sub-signal, splicing the first sub-signals in combination with the target position operation of each first channel to obtain a trigger signal, and sending the trigger signal to the functional board card through a second channel; the target bit operation is used for shifting the data received by each first channel, so that each piece of data in the processing result for the same sending moment is aligned; and the function board card is used for receiving the trigger signal and sending an execution signal aiming at the quantum bit to the quantum chip, so that the quantum chip executes the quantum calculation task. Low delay of data transmission among modules can be realized, and the stability of data transmission is ensured.

The present application relates to the field of computer application technology, and provides a method and hardware architecture for obtaining the greatest common divisor of large number expansion, including a control module, a GCD calculation unit, a Bézouté coefficient calculation unit, a first multiplexer, a second multiplexer, a termination module, and an input_valid signal. The GCD calculation unit and the Bézouté coefficient calculation unit are used to iteratively update intermediate variables according to the control signal of the control module. By introducing the δ parameter, the comparison of the sizes of the intermediate variables a and b is avoided. Based on the k-ary algorithm, the calculation and redundant form of the Bézouté coefficient are introduced. In hardware implementation, only simple addition, subtraction, and shift operations are required, which greatly reduces the time required for addition operations, thereby achieving the purpose of increasing the clock frequency, reducing the iteration cycle, and shortening the total running time.

The present invention provides an FPGA multiplier optimization method, which detects the actual effective bit width of data at two input ends, generates a bit width control signal, and selects a small bit width parallel calculation mode or a full bit width calculation mode based on the bit width control signal; in the small bit width parallel calculation mode, multiple groups of input data with effective bits of small bit width are sign-bit extended to generate parallel calculation data including sign bits, and the generated parallel calculation data are shifted and spliced ​​before being sent to a multiplier for parallel calculation; in the full bit width calculation mode, the data directly enters the multiplier for calculation. The present invention also provides an FPGA multiplier optimization device.

A computing device (101), method and computer program product herein for replicating a three-dimensional label mask (20) for a three-dimensional volumetric data set (190) in a network (100) of computing devices. The device (101) receives, from a further computing device (102) of the network, a series of segmented input data (21) describing an edit (2-1) of a tag mask (20) on the further computing device (102). The segment input data includes current location data, size data, and a tag identifier associated with a spherical segment object (102-1) used by the second computing device (102) to interactively edit the tag mask. A replicator module (101-10) replicates an edited tag mask of the further computing device (102) associated with the series of segmented input data by: calculating a respective ellipsoid corresponding to the spherical segmented object (102-1) stretched inversely proportional to the shape of voxels in the tag mask; determining voxels (vi) of a label mask having positions inside the segmented object on the basis of the ratio of the distance between the respective voxel position and the center position of the ellipsoid divided by the respective semi-axis length of the ellipsoid in all three dimensions, wherein the division is performed using a bitwise operation on a graphics processing unit of the computing device (101) to invert an index of each denominator; and updating the determined voxels in the replicated tag mask (10) in accordance with the tag identifier of the segmented input data (21).

The invention provides a method and a device for solving a time error in 2038. The method comprises the following steps: aiming at the condition that a kernel version of an operating system is smaller than a first preset version, responding to a first operation of a user, setting 64-bit time to obtain system calling and 64-bit time setting system calling, so that an application program obtains and sets 64-bit time, the bit number of RTC time is modified into 64 bits, and kernel time of the operating system comprises 64-bit time; when the application program is in the running state, the application program processes 64-bit time through a preset 64-bit time processing function, and the preset 64-bit time processing function is set in a source code of the application program. According to the method and the device, the operation system can directly process the 64-bit time by using the original kernel version without upgrading the kernel version, the scheme is simple, and the difficulty of processing the 64-bit time by the operation system is reduced.

The invention provides a data processing method and device, and the method comprises the steps: obtaining to-be-processed data and a target weight, the target weight comprises a plurality of groups of effective numerical value sequences, and the numerical value of each group of effective numerical value sequence is a power value of each power of 2 after the initial weight is converted into the sum of a plurality of power of 2; based on the target weight, at least one target shift number is obtained, and each target shift number is a numerical value of all or part of the effective numerical value sequence in the target weight; executing the first strategy, and obtaining a processing result of the to-be-processed data based on the obtained second shift result; wherein the first strategy comprises the following steps: splitting each target shift number into the same common shift number and the respective independent shift number based on the maximum shift number of a single shift operation supported by hardware; performing first-level shift on the data to be processed by a plurality of independent shift numbers and then adding to obtain a first shift result; and performing secondary shifting on the first shifting result according to the common shifting number to obtain a second shifting result.

A resource allocation method and device based on bitmap precalculation, the method comprising: generating a global resource state bitmap according to CORESET configuration in a PDCCH, precalculating a candidate pre-allocation bitmap set for each possible candidate PDCCH; extracting a corresponding pre-allocation bitmap from the candidate pre-allocation bitmap set as a candidate set bitmap; comparing the candidate set bitmap with the global resource state bitmap to determine whether the resources conflict, if the resources do not conflict, the resources are available, and then the resources are occupied. The present application transfers the complex function calculation at the scheduling time to the precalculation in the initialization stage, only needs simple bitmap retrieval and bit operation at the scheduling time, greatly shortens the PDCCH resource allocation time consumption, replaces the real-time intensive calculation by pre-storing the bitmap, significantly reduces the CPU load, focuses the processor on the core scheduling algorithm, reduces the resource redundancy consumption, and effectively improves the overall capacity and energy utilization efficiency of the communication system.