59 results about "Bit manipulation" patented technology

The invention discloses a resource allocation method and device based on bit map pre-calculation, and the method comprises the steps: generating a global resource state bitmap according to the CORESET configuration in a PDCCH, and carrying out the pre-calculation of each possible candidate PDCCH to form a candidate pre-allocation bit map set; extracting a corresponding pre-allocation bitmap from the candidate pre-allocation bitmap set as a candidate set bitmap; and comparing the candidate set bitmap with the global resource state bitmap, judging whether the resources are conflicted or not, and if the resources are not conflicted, determining that the resources are available and further occupying the resources. Complex function calculation at the scheduling moment is transferred to pre-calculation at the initialization stage, only simple bitmap retrieval and bit operation are needed during scheduling, the PDCCH resource allocation time consumption is greatly shortened, real-time intensive calculation is replaced with pre-stored bitmaps, the CPU load is remarkably reduced, a processor focuses on a core scheduling algorithm, resource redundancy consumption is reduced, and the scheduling efficiency is improved. And the overall capacity and the energy utilization efficiency of the communication system are effectively improved.

To automatically test an OS incorporated in equipment or a control board.SOLUTION: An acquisition unit 51 that communicates with a repository via a network and acquires a source code of a target program from the repository, a build unit 52 that builds the target program using the acquired source code, a writing unit 53 that performs a process of writing the built target program to a storage unit of a target board, a reset unit 54 that performs a process of resetting the target board, a communication unit 55 that communicates with the target board, instructs a control unit of the target board to execute an automatic test, and receives a test result of the automatic test from the target board, and a determination unit 56 that performs a process of determining results of various tests executed on the target board based on the received test result.SELECTED DRAWING: Figure 6

The invention relates to an implementation method for applying linear subcomponents of a ZUC algorithm to multiple scenes. The method comprises the following steps: constructing a linear transformation matrix expression from an input bit sequence to an output bit sequence of a linear subcomponent according to the definition of the linear subcomponent in the ZUC algorithm; and carrying out structure division on the linear transformation matrix expression, and decomposing the original large-scale matrix operation into at least two independent small-scale matrix operations. And according to each small-scale matrix design, a logic gate level implementation scheme based on in-situ XOR operation is designed, and a bit operation sequence is generated. And mapping the logic gate-level implementation scheme into a plurality of physical circuit modules with a hierarchical connection relationship according to the data dependency relationship among the bit operation sequences, so that all the physical circuit modules jointly form a component structure suitable for multiple scenes. By adopting the method, the reliability and applicability of the communication system or equipment for executing the ZUC algorithm can be enhanced.

A calculator for calculating a plurality of square roots includes a memory array, at least two registers, a bit subtractor, and a controller. The memory array is organized into columns and rows. The registers store a fixed value. The controller, operatively coupled to the other components, allocates a first set of rows to test variables and a second set to result variables, and initially stores each of a plurality of radicands in a separate column. For multiple iterations, the controller concurrently activates selections of rows to form current operands and current guesses for each column. The controller then instructs the bit subtractor to perform subtraction operations. For each column with a positive subtraction result, the controller selectively writes a new bit of the square root and selectively overwrites values with a new remainder derived from the subtraction result, without performing an explicit data-shifting operation.

The invention relates to a DAC digital calibration circuit and an implementation method thereof, and the circuit comprises a multiplier which is used for receiving DAC original conversion data and a slope calibration parameter for multiplication operation, and outputting a result bit width which comprises a DAC bit width and a calibration parameter bit width; the shift register is used for performing shift operation on the result output by the multiplier to obtain a decimal multiplication result to complete slope calibration; the adder is used for adding the decimal multiplication result output by the shift register with the zero calibration parameter and trimming the zero error; the selector is used for receiving an output result of the adder; if the high-order data is not 0, full-scale data of all 1 codes are selected to be output; otherwise, selecting the summator to output the result; and the data register is used for registering the result output by the selector. According to the invention, actual measurement analysis is carried out on the chip behind the flow sheet, then calibration and trimming parameters are determined, inherent errors of the chip are compensated, and higher precision is realized.

The invention discloses a binary MDS array code structure with high erasure correction performance and a decoding method, and the decoding method achieves the rapid calculation of a syndrome vector through an optimized scheduling algorithm, only needs the exclusive or and cyclic shift operation, reduces the calculation complexity to a linear level O (n), and remarkably improves the data recovery speed. Compared with a traditional RS code and an existing array code, high reliability is guaranteed, the technical problem that storage efficiency and calculation complexity are difficult to consider at the same time is solved, and the method is suitable for large-scale distributed storage scenes such as cloud computing and artificial intelligence training. According to the binary MDS array code structure with the high erasure performance and the decoding method, the fault-tolerant capability is improved to five-node failure, and the high-reliability storage requirement is met; the decoding calculation complexity is obviously reduced, and only xor and shift operations are needed; the storage efficiency reaches the upper bound of the MDS theory, and the storage cost is reduced; and efficient data recovery is realized under the configuration that the code length n is equal to 11 and the redundancy r is equal to 5.

A method and apparatus for reducing computation time are disclosed herein which provides in at least one embodiment a computer-implemented method for reducing computation time, the computer-implemented method including the steps of: receiving one or more bits from a multiplier, generating a shift signal by using the one or more bits, performing a shift operation by n bits (where n is a natural number) based on the shift signal to obtain a partial product, and generating an output product by using the partial product and then outputting the output product.

A resource allocation method and device based on bitmap precalculation, the method comprising: generating a global resource state bitmap according to CORESET configuration in a PDCCH, precalculating a candidate pre-allocation bitmap set for each possible candidate PDCCH; extracting a corresponding pre-allocation bitmap from the candidate pre-allocation bitmap set as a candidate set bitmap; comparing the candidate set bitmap with the global resource state bitmap to determine whether the resources conflict, if the resources do not conflict, the resources are available, and then the resources are occupied. The present application transfers the complex function calculation at the scheduling time to the precalculation in the initialization stage, only needs simple bitmap retrieval and bit operation at the scheduling time, greatly shortens the PDCCH resource allocation time consumption, replaces the real-time intensive calculation by pre-storing the bitmap, significantly reduces the CPU load, focuses the processor on the core scheduling algorithm, reduces the resource redundancy consumption, and effectively improves the overall capacity and energy utilization efficiency of the communication system.

This disclosure provides a data shifting operation method, apparatus, electronic device, and storage medium, relating to the field of data operation technology. The method includes: splitting a source operand into multiple sub-operands according to its bit width, determining the shift direction based on the shift type, and determining the segmented shift processing method based on the target shift amount, so that multiple shifting operation units perform shift operations on each sub-operand respectively; further, combining and concatenating the shift results across segments to obtain the target shift result. This technical solution, by transforming the shifting of high-bit-width data into a collaborative processing process of multiple low-bit-width data, and employing differentiated processing paths under different shift ranges, can reduce circuit implementation complexity, reduce hardware resource consumption, improve the reusability of shifting operation units, and enhance the flexibility and adaptability of the system structure while ensuring the consistency of shift semantics.

The invention discloses a short character string monotonic order-preserving materialized compression coding method, which comprises the following steps of: performing a series of bit operations such as byte inversion, length information embedding, logic right shift and high-order mask shielding on an original variable-length character string with a limited length, and losslessly mapping the original variable-length character string into a fixed-length integer value; the lexicographical order of the character string before and after mapping is completely consistent with the numerical order of the integer; according to the method, the fixed-length integer code is used for directly replacing an original character string to participate in sequencing, aggregation and comparison operation of the database, so that the problems of branch prediction failure, discontinuous memory access, vectorization difficulty and the like caused by processing variable-length data in a traditional scheme are greatly avoided, the memory occupancy is greatly reduced, and meanwhile, the vectorization efficiency is improved. And the CPU execution efficiency and the cache utilization rate are greatly improved.

The invention discloses a note positioning method and device, electronic equipment and a storage medium, and relates to the technical field of computers, in particular to the field of artificial intelligence such as natural language processing and intelligent documents. According to the specific implementation scheme, in response to detection of a backtracking positioning operation for a target note displayed in a first page, source positioning information of the target note is obtained; determining a target source of the target note according to the source positioning information; loading and displaying the target source in a second page; and controlling a display window of the second page to roll to a corresponding position of the target note in the target source according to the source positioning information.

This invention discloses a native parallel data packing method for 64-bit CPUs, belonging to the field of computer data representation and processing technology. This method packs eight 8-bit raw data columns into a standard 64-bit register, with each data column including 6 data bits and 2 carry bits. The raw data is expanded into a 64-bit data column through a bit extension step, and then packed into the 64-bit register using bit manipulation instructions to form 64-bit packed data. Inline functions are used to achieve zero function call overhead. The compiler automatically optimizes and generates efficient machine code, requiring no SIMD instruction set support. A lookup table method is used to achieve zero computational overhead packing; the lookup table contains 4096 entries. 64-byte cache row alignment is used to improve cache hit rate. Compared to traditional methods, packing and unpacking overhead is reduced by 6.6 times, from 11.3 ms to 1.7 ms. L1 cache hit rate is increased from 65% to 95%, memory access latency is reduced from 45 cycles to 12 cycles, and memory performance is improved by 3.75 times.

This application provides a method, circuit, apparatus, electronic device, and readable storage medium for constructing a shuffle logic circuit, comprising: arranging an input conversion interface according to the bit width information of the data to be processed; designing a selector architecture according to the bit width information, the selector architecture including a decoder and a multi-level selection unit, the decoder being used to uniformly decode and generate control signals which are then input to the multi-level selection unit; the selector architecture being used to select and shift data bit groups to obtain shuffled recombined data; and constructing a shuffle logic circuit based on the input conversion interface and the selector architecture. Compared with related technologies, this application significantly reduces the circuit physical area and power consumption.

The invention provides a data processing method and device for in-network calculation, and the method comprises the steps: carrying out the format analysis of first data and second data based on a first preset bit width, unifying the bit width standard of the input data, solving the compatibility problem of a heterogeneous data source, enabling the adaptive first update data and second update data to be directly connected with a hardware acceleration unit, and enabling the data to be more uniform. And additional conversion overhead caused by bit width mismatching is avoided. The first updating data and the second updating data are split according to the second preset bit width, the precision range of an intermediate calculation result can be controlled, the overflow risk caused by direct multiplication of high-bit-width data is avoided, data partitioning processing is achieved, multiplication operation can be executed in parallel, the data size of single-time processing is reduced, the memory bandwidth pressure is reduced, and the data processing efficiency is improved. And the throughput of output processing is greatly improved. Product term accumulation is realized through a shift summation mode, and in combination with a hardware-friendly bit operation, multiplier resource occupation can be reduced, calculation delay can be reduced, and a pipeline calculation architecture can be adapted.

A method of performing a convolution operation is provided. The method includes obtaining a lightweight convolutional neural network with a reduced bit width of weights, and inputting input data to the convolutional neural network and performing neural network computations to obtain output data. The neural network computations includes determining a shift distance based on a value of input feature data, performing a shift operation to reduce a bit width of the input feature data based on the shift distance, performing a convolution operation on the input feature data with the reduced bit width and the weights with the reduced bit width, wherein the convolution operation includes a shift operation of restoring the bit width, and obtaining output feature data with the restored bit width.

A method of performing logical qubit operations 27,29,31,33 on an ensemble of logical qubits 1a-d, each logical qubit having a plurality of physical qubits. The method comprising: performing one or mo

The invention discloses a 32-bit processor based on an RISC-V instruction set architecture, and belongs to the field of computer system structures and microprocessor design. According to the technical scheme adopted by the invention, the 32-bit processor based on the RISC-V instruction set architecture comprises an instruction set extension module, two new instructions of'aggresgate 'and'disaggresgate' are introduced, an R-type coding format is adopted, and the 32-bit processor is used for realizing grouping and splitting operation of data bits; the data path unit comprises a general register group, an arithmetic logic unit ALU and a special adder and is used for executing various data operations and processing; the control unit is used for generating a control signal according to an instruction decoding result and controlling operation of the data path unit and the memory; according to the method, by adding the special instruction and optimizing the data flow control mechanism, the complex bit operation is completed in a single period, the cache pressure is reduced, and the method has the advantages of improving the bit operation efficiency, reducing the instruction cache pressure and reducing the dynamic power consumption.

The application discloses a high-parallel rejection sampler for post-quantum cryptography and a working method thereof, and eight bits of to-be-sampled data are split into symmetric high-4-bit and low-4-bit parallel sampling units: the high-4-bit unit performs data compression in the direction of the least significant bit, and the low-4-bit unit performs data compression in the direction of the most significant bit; two-way compression outputs are combined through a physical splicing mode to form pre-alignment data flow with intermediate features of data continuity and possible invalid data bits at the head and tail. Subsequently, the system uses the valid data count value of the high-bit unit as a control signal to drive a multi-way selector network to directly select an output result according to five preset alignment paths, so that compact arrangement of full-parallel data is realized. The application avoids complex multi-stage shift operations in a traditional architecture, greatly optimizes key path delay and hardware resource overhead, and is suitable for high-speed hardware accelerator design of post-quantum cryptography algorithms.

The invention relates to the field of microcontrollers, in particular to the field of industrial control, and specifically relates to an MCU device with portability and low power consumption. The MCU device with portability and low power consumption comprises an instruction architecture, a storage architecture and a pipeline architecture in the aspect of a kernel; an instruction architecture, a storage architecture and a pipeline architecture are simplified; in the aspect of peripherals, design is carried out according to requirements in current industrial scenes, modules such as a UART (Universal Asynchronous Receiver / Transmitter), an SPI (Serial Peripheral Interface) and a TMR0 are modularized, and implementation is carried out based on an SFR bus protocol; a simplified instruction system structure is used, and a PIC16F8X series instruction system is compatible; classifying the instruction into a file register byte-oriented operation type instruction, a file register bit-oriented operation type instruction, an immediate operand operation type instruction and a fixed coding format control type instruction according to different instruction types; in all the operation instructions, the operation code field is located in the highest bit field, and information report instruction types and function information are contained in the operation code field.

The present disclosure relates to a method and device for data processing using a photon-electron hybrid computing system, the method comprising: performing a first shift operation on a first multiplier and a second multiplier to be input into a photon multiplication unit, so that the bit width of the multipliers is the same as the bit width supported by the photon multiplication unit; storing the first multiplier and the second multiplier subjected to the first shift operation into a first buffer and a second buffer respectively, and having a first index value and a second index value respectively; obtaining the multipliers to be multiplied from the buffers and inputting them into the photon multiplication unit for multiplication processing to obtain a multiplication result; storing the multiplication result into a third buffer and having a third index value, which is the sum of the first index value and the second index value; and performing a second shift operation on the multiplication result, the shift direction of which is opposite to that of the first shift operation, and the shift bit number is the third index value. Thus, multiplication operation of input numbers with any bit width can be realized.

This application proposes a control method for a phase-change memory (PCM) and a PCM itself. The method includes: obtaining the number of memory cells; and, if the number of memory cells is less than a threshold value, performing a first reset operation on a first target memory cell among the multiple memory cells. The first reset operation includes: applying a first word line voltage to a first word line coupled to the first target memory cell during a first time period, and applying a first word line voltage and a first current to the first bit line coupled to the first target memory cell; applying a second word line voltage to the first word line during a second time period, and applying a first word line voltage and a first current to the first bit line, wherein the second word line voltage is greater than the first word line voltage; and applying the second word line voltage to the first word line during a third time period, and applying a first word line voltage and a second current to the first bit line, wherein the second current is greater than the first current. This method can reduce overcharge current in the PCM.

The invention relates to the technical field of electronic countermeasures, in particular to an FPGA (Field Programmable Gate Array)-based post-pulse-compression environment self-adaptive dynamic bit cutting method. The method comprises the steps of data storage, symbol detection, exception processing, position calculation, adaptive bit interception and the like. When a radar system is powered on or calibration is executed, the surrounding environment is actively scanned, pulse compression output data in each beam direction are collected, and the maximum echo amplitude in each beam direction is extracted; and based on the maximum value, dynamically calculating an optimal truncation start bit of the corresponding beam. Real-time calculation or feedback adjustment is not needed, the whole process only relates to simple bit operation, the time sequence allowance is sufficient, and resource consumption is extremely low.

The application discloses a kind of dynamic program analysis methods for WOW64 environment enhancement, can be carried out to the target application program of high-efficiency fine-grained analysis under the running of WOW64 environment, fusion 64-bit Windows operating system built-in simulator realizes the high-efficiency stable analysis of 32-bit and mixed program, while compatible 64-bit mode execution code analysis, using system kernel characteristics realizes the interception and dynamic insertion of target program execution, and proposes the dynamic analysis code generation scheme for WOW64 environment enhancement, reduce the influence on target program execution, with good deployability.The application realizes the dynamic program insertion of system kernel driver and analysis method, optimization is carried out to the analysis scene under the WOW64 environment, can realize the dynamic analysis of multiple types of programs.The application improves the availability of dynamic analysis in the WOW64 environment, further improves the performance of fine-grained analysis and analysis detection confrontation ability.

According to an embodiment, a method performed by a distributed unit (DU) may comprise generating, based on a modulation compression scheme, a modulation value corresponding to information bits. The method may comprise generating, based on a shifting operation corresponding to the modulation compression scheme, user plane (U-plane) data corresponding to the modulation value. The method may comprise transmitting, to a radio unit (RU) through a fronthaul interface, a U-plane message comprising the generated U-plane data. In a case of binary phase shift keying (BPSK), the modulation compression scheme may be set to perform the shifting operation based on a designated first equation. In a case of non-BPSK, the modulation compression scheme may be set to perform the shifting operation based on a designated second equation.

A method, system and computer program product for computing noise channels for multi-qubit quantum operations. The learned Lindbladian describing the dynamics of a multi- qubit operation is received. The learned Lindbladian refers to a Lindbladian operator that has been derived or learned from data, such as low-weight observable measurements. The learned Lindbladian is then analyzed, such as using the ideal gate Hamiltonian (Hg) on n qubits, to identify the noise terms. A noise channel is then computed using a perturbative approach based on the identified noise terms. Examples of the perturbation approach include the Mangus expansion or the Dyson expansion. By using such a perturbative method to compute the noise channel, such a computation is performed in a controlled manner which exploits the locality of noise to reduce the complexity yet results in an accurate noise channel that correctly predicts how the physical noise acts on the qubits.

The application discloses a dynamic vector mask generation and control flow optimization method and device, and relates to the technical field of computers. The method comprises the following steps: acquiring and analyzing bit-level condition expression information in an executed program; extracting, rearranging or combining a target bit to generate a compact bit vector representing an execution condition of a target data element; performing format conversion on the compact bit vector based on a vector configuration parameter to generate a vector mask adapted to the current vector register layout; controlling the execution behavior of the target data element based on the vector mask; and adaptively adjusting the vector mask when the vector length changes. By constructing a mapping relationship between the bit-level condition and the vector mask, the direct control of the bit operation result on the vector execution is realized, the mask generation overhead and the control flow branch overhead are reduced, and the vector execution efficiency is improved.

The application discloses a phase change memory and an operating method. The phase change memory comprises a word line, a bit line and a storage module. The word line and the bit line to which a reverse voltage difference is applied are connected in a set operation through the storage module, so that the threshold voltage of the storage module can be reduced. Thus, the difference between the threshold voltage of the storage module after a reset operation and the threshold voltage of the storage module after a set operation can be increased while keeping the threshold voltage of the storage module after the reset operation unchanged, and the read window margin is improved.

The invention discloses an ROM automatic test circuit and a test method thereof, and belongs to the technical field of integrated circuit design. Comprising an ROM controller, an MISR module, an interface module and a TAP controller. The ROM controller interacts with the interface module; the MISR module is used for compressing the storage data read from the ROM through a bit operation compression algorithm to obtain a feature test value, and the bit operation compression algorithm processes the data through a specific bit operation rule; the interface module is used for performing synchronization and logic processing on a control signal, reducing power consumption through clock gating design, and performing controllable design on a circuit so as to improve the coverage rate during scanning test; and the TAP controller is used for realizing entry of an ROM test mode, capturing a characteristic test value and outputting the characteristic test value for external comparison. The ROM testing method and device can solve the problems that traditional ROM testing needs hardware iteration and is complex in process, have the advantages of being high in testing efficiency, high in compatibility and the like, and are particularly suitable for ROM testing in a large-scale integrated circuit.

A memory device includes a phase change memory (PCM) cell connected between a bit line and a word line. An X-decoder provides a word line voltage to the word line during a reset operation, and a Y-decoder provides a bit line voltage to the bit line during the reset operation. A voltage bias circuit generates the word line voltage and the bit line voltage based on a first bias during a first period of the reset operation, the word line voltage and the bit line voltage based on a second bias greater than the first bias during a second period of the reset operation, and the word line voltage and the bit line voltage based on a third bias smaller than the first and second biases during a third period of the reset operation. Fig. 1

The invention relates to a cross-platform bit reverse order implementation method, and belongs to the technical field of software. The method comprises the following steps: defining a bit field structural body; defining two bit field structural body variables A and B; copying the data variable to be converted into the structural body variable A; assigning a low-order member in A to a corresponding high-order member in B through a member variable assignment mode of a bit field structural body; and copying the structural body variable B into the converted data. Compared with a traditional shifting operation mode for achieving bit field reverse order, the method has the advantages that the execution time is shortened by nearly 40%, and the execution efficiency of codes is greatly improved.