Time synchronization method and device among multiple FPGAs, equipment and storage medium

Abstract

The invention discloses a time synchronization method and device among multiple FPGAs, equipment and storage medium, and the method comprises the steps of receiving IRIGB time coding information of anexternal IRIGB code clock source through a timing main station FPGA, carrying out the B code timing and punctuality, and obtaining the calibrated synchronization time information and microsecond clock pulse; using the timing master station FPGA to send the synchronization time information to each timing slave station FPGA through an SPI bus at the same time, and sending the microsecond clock pulse to each timing slave station FPGA through a GPIO hard connection line at the same time; and receiving the synchronous time information by the FPGA of each timing slave station to perform local timing, and receiving the microsecond clock pulse to perform local timing. Therefore, precious logic of the FPGA is effectively saved, meanwhile, the timing precision and the synchronism among a pluralityof board-level devices can be guaranteed, and resource waste caused by independent timing in each FPGA is avoided.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a time synchronization method, device, equipment and storage medium among multiple FPGAs. Background technique [0002] In a board-level circuit, if multiple devices need time synchronization, for example, a certain type of distributed control system (Distributed Control System, DCS) master contains multiple Profibus-DP (Process Field Bus-Decentralized Periphery) master stations, in three On-chip Field Programmable Gate Array (Field-Programmable GateArray, FPGA), each Profibus-DP needs to carry out precise synchronous time information communication. [0003] In the prior art, usually the figure 1 with figure 2 way to achieve: such as figure 1 As shown, the IRIG-B time coding signals are respectively connected to three FPGAs, and the time calibration management is carried out independently through the B code timing algorithm module in the FPGA; figure 2 As shown, in t...

AI Technical Summary

Problems solved by technology

However, for the method of Figure 1, because of the timing logic It is more complicated and takes up more logic resources, and it is implemented in multiple FPGAs separately, resulting in waste of resources; at the same time, the clocks of each FPGA are different, resulting in asynchronous time between each other

For the method of Figure 2, NTP timing mainly depends on software Algorithm to ensure that sending time information through LocalBus is also time-sharing, so both time accuracy and time synchronization are relatively low

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