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Configurable multiplication device applied to AES and RSA mixed algorithm hardware circuit

A hardware circuit, hybrid algorithm technology, applied in encryption devices with shift registers/memory, secure communication devices, electrical components, etc., can solve the problems of cost, multiple circuit area and logic, etc.

Active Publication Date: 2017-10-10
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The mixed encryption algorithm based on AES and RSA algorithm is widely used. For the operation circuit of the two algorithms, if the special circuit of the two algorithms is simply integrated, it will consume more circuit area and logic.

Method used

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  • Configurable multiplication device applied to AES and RSA mixed algorithm hardware circuit
  • Configurable multiplication device applied to AES and RSA mixed algorithm hardware circuit

Examples

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Embodiment Construction

[0018] figure 1 Shown is a block diagram of the internal structure of a configurable multiplication device that can be used in AES and RSA mixed algorithm hardware circuits of the present invention. The device organizes multipliers and adders according to a special structure to realize configurable AES column mixing and RSA 64bit multiplication. In the figure, a 16-bit dual-field multiplier is realized by using four 8-bit dual-field multipliers, one 32-bit dual-field 4-2 compressor and one 32-bit dual-field look-ahead carry adder; and then four 16-bit dual-field multipliers , 1 64bit dual-field 4-2 compressor and 1 64bit dual-field look-ahead adder to realize 32bit dual-field multiplier; 4 32bit dual-field multipliers, 1 128bit dual-field 4-2 compressor and 1 A 128bit double-field look-ahead adder implements a 64bit double-field multiplier. Therefore, the implementation scheme shown in the figure includes the following 4 parts: 1. Multiplier array composed of 64 8bit multipl...

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Abstract

The invention discloses a configurable multiplication device of which hardware implementation can be applied to an AES and RSA mixed algorithm hardware circuit, and belongs to the field of cryptographic algorithm hardware implementation. Compared with an implementation scheme based on an ordinary multiplier in the past, the device has the advantages that a large number of configurable circuits are adopted by designing a special circuit structure, large-area multipliers and adders are reused, an AES MixColumn function and an RSA multiplication function are achieved in one operational circuit on the basis of additionally consuming a small number of selectors, and compared with the method of implementing the two kinds of operation singly, less circuit area is consumed, and less logic is used.

Description

technical field [0001] The invention relates to the field of network data security, and specifically belongs to the field of cryptographic algorithm hardware implementation. Background technique [0002] The AES (Advanced Encryption Standard, AES) encryption algorithm, also known as the Rijndael algorithm, was proposed by the National Institute of Standards and Technology (NIST) in 2001 to replace the DES that had been broken at that time ( Data Encryption Standard, DES) encryption algorithm. AES is a widely used symmetric encryption algorithm, which uses the same key for encryption and decryption. [0003] RSA (Rivest Shamir Adleman, RSA) algorithm was proposed by Ron Rivest, Adi Shamir and Leonard Adleman in 1977, and named after three people. RSA is an asymmetric cryptographic algorithm that uses different keys for encryption and decryption. [0004] The hybrid cryptographic algorithm based on AES and RSA combines the advantages of both AES and RSA, and has been applie...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06H04L9/30
CPCH04L9/0631H04L9/302
Inventor 李冰杨宇高洲顾巍刘勇沈克强王刚赵霞董乾张林陈帅
Owner SOUTHEAST UNIV
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