On-chip heterogeneous multi-core system based on star type interconnection structure, and communication method thereof

A heterogeneous multi-core, architecture technology, applied in the fields of instruments, electrical digital data processing, computers, etc., can solve the problems of increasing the difficulty of layout and wiring, hardware overhead, and many hardware resources, and achieve the effect of reducing logic and improving throughput.

Active Publication Date: 2012-11-28
SUZHOU INST FOR ADVANCED STUDY USTC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This interconnection method generally has relatively high scalability, but it takes up more hardware resources, which will increase the difficulty of layout and wiring and hardware overhead.
In general, the scalability, high performance, and low overhead of the current on-chip interconnect structure are difficult to meet at the same time

Method used

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  • On-chip heterogeneous multi-core system based on star type interconnection structure, and communication method thereof
  • On-chip heterogeneous multi-core system based on star type interconnection structure, and communication method thereof
  • On-chip heterogeneous multi-core system based on star type interconnection structure, and communication method thereof

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Embodiment

[0036] Such as figure 1 As shown, the on-chip heterogeneous multi-core system obtained in this embodiment is composed of a core scheduling processor 3, 3 computing processors 1 and 3 IP cores 2, and the core scheduling processor is connected to the computing processor and the IP core. The on-chip bus based on the point-to-point bus is used for interconnection, and the message transmission between the core scheduling processor and the computing processor is based on the communication model of the interconnection architecture. The communication model is implemented using a non-blocking interface. The core scheduling processor is responsible for receiving task requests from users, and sending the task requests to computing processors through the interconnection structure. The calculation processor is responsible for receiving task requests from the core scheduling processor and performing task calculations. The on-chip network based on the point-to-point bus is used for interco...

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Abstract

The invention discloses an on-chip heterogeneous multi-core system based on a star type interconnection structure, and a communication method thereof. The system comprises a core scheduling processor, at least one calculation processor and at least one hardware IP core, and is characterized in that a chip network based on a point-to-point bus is respectively used between the core scheduling processor and the calculation processor and between the core scheduling processor and the hardware IP core for interconnection so as to form a star type interconnection structure; message transmission is carried out on a communication model based on the star type interconnection structure between the core scheduling processor and the calculation processor; and the communication module is realized by using a non-blocking interface. The system improves the throughput rate and the expandability of the access.

Description

technical field [0001] The invention belongs to an on-chip multi-core heterogeneous system, in particular to an on-chip heterogeneous multi-core system based on a star interconnection architecture and a communication model used therefor. Background technique [0002] Since the interconnection strategy has a great influence on the performance of the system on chip, and the reconfigurable system requires the hardware platform to have strong scalability, the resource-constrained hardware platform of Field Programmable Gate Array (Field Programming GateArray, FPGA) In general, how to choose an efficient, scalable, and low-overhead interconnection architecture is an important issue for System on Chip (SoC) designers and developers to study. There are two mainstream on-chip high-efficiency communication mechanisms, one is based on the structure of bus shared storage (mainly Cache), and the other is based on other on-chip interconnection structures such as crossbar switches. [00...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
Inventor 周学海王超张军能冯晓静李曦陈香兰
Owner SUZHOU INST FOR ADVANCED STUDY USTC
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