On-chip heterogeneous multi-core system based on star type interconnection structure, and communication method thereof

Abstract

The invention discloses an on-chip heterogeneous multi-core system based on a star type interconnection structure, and a communication method thereof. The system comprises a core scheduling processor, at least one calculation processor and at least one hardware IP core, and is characterized in that a chip network based on a point-to-point bus is respectively used between the core scheduling processor and the calculation processor and between the core scheduling processor and the hardware IP core for interconnection so as to form a star type interconnection structure; message transmission is carried out on a communication model based on the star type interconnection structure between the core scheduling processor and the calculation processor; and the communication module is realized by using a non-blocking interface. The system improves the throughput rate and the expandability of the access.

Description

technical field [0001] The invention belongs to an on-chip multi-core heterogeneous system, in particular to an on-chip heterogeneous multi-core system based on a star interconnection architecture and a communication model used therefor. Background technique [0002] Since the interconnection strategy has a great influence on the performance of the system on chip, and the reconfigurable system requires the hardware platform to have strong scalability, the resource-constrained hardware platform of Field Programmable Gate Array (Field Programming GateArray, FPGA) In general, how to choose an efficient, scalable, and low-overhead interconnection architecture is an important issue for System on Chip (SoC) designers and developers to study. There are two mainstream on-chip high-efficiency communication mechanisms, one is based on the structure of bus shared storage (mainly Cache), and the other is based on other on-chip interconnection structures such as crossbar switches. [00...

AI Technical Summary

Problems solved by technology

This interconnection method generally has relatively high scalability, but it takes up more hardware resources, which will increase the difficulty of layout and wiring and hardware overhead.

In general, the scalability, high performance, and low overhead of the current on-chip interconnect structure are difficult to meet at the same time

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