44 results about "Interconnection architecture" patented technology

The invention relates to a transportation junction multi-business micro-energy network chain-type interconnection architecture, and the architecture comprises a load layer which comprises micro-energy networks of different business forms; the energy layer comprises an external energy source and a distributed power generation and energy storage system and is used for providing comprehensive energy supply for energy consumption requirements of the micro-energy grids in different commercial forms in the load layer; the energy network layer comprises different types of energy networks, the different types of energy networks carry out coupling conversion on energy of the energy layer so as to meet the energy use requirements of micro energy networks in different business states in the load layer, and coupling interaction and interconnection intercommunication between the different types of energy networks are achieved through different types of energy conversion equipment; and the cloud edge-end energy collaborative management and control system is used for regulating and controlling the energy layer, the energy network layer and the load layer by utilizing a cloud-edge-end three-layer management and control architecture so as to realize the collaboration and dynamic balance of multiple energy flows among different regions of the transportation hub.

The invention discloses a resource scheduling method, an electronic device, a medium and a product, and relates to the technical field of AI intelligent computing, and the method comprises the steps: obtaining the bandwidth utilization rate of a main switching device in a plurality of switching devices through a host, and if the bandwidth utilization rate of the main switching device is greater than a first preset utilization rate, executing the first preset utilization rate; if yes, whether standby switching equipment meeting a preset standby condition exists in the remaining switching equipment except the main switching equipment in the multiple pieces of switching equipment or not is queried based on a first circular query strategy, and if not, a target switching equipment meeting a preset transmission condition is determined from the multiple first switching equipment, the to-be-calculated data is stored in the shared memory pool through the target switch, and low congestion, high throughput and high resource utilization rate under large-scale AI training and reasoning tasks are realized by introducing multi-level popularity perception, dynamic threshold adjustment, standby path switching and cross-network data unloading mechanisms into a hybrid interconnection architecture of the shared memory pool.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

The invention belongs to the technical field of optical fiber communication, and discloses an internal and external optical interconnection architecture of a chip. The chip internal and external optical interconnection framework comprises a printed circuit board, a glass substrate, a chip unit and an external optical interface. The glass substrate is arranged above the printed circuit board, the chip unit is arranged above the glass substrate, and the external optical interface is arranged on the side surface of the glass substrate; a rewiring layer and an optical waveguide are arranged in the glass substrate, and the rewiring layer is arranged below the chip unit; the chip unit comprises a main chip, a storage chip, an electronic integrated chip and a photonic integrated chip; the photonic integrated chip is optically coupled with an external optical interface through an optical waveguide. The invention further provides a manufacturing method of the chip internal and external optical interconnection architecture. The chip internal and external optical interconnection architecture is the chip internal and external optical interconnection architecture. According to the invention, the electrical interconnection distance of high-speed data transmission can be greatly shortened, the transmission rate and the signal quality are improved, and the device power consumption is reduced.

The invention relates to the technical field of industrial network communication, in particular to an SDN (Software Defined Network) industrial network routing method based on deep traffic classification and dynamic pheromone optimization. According to the method, an SMOTE algorithm is improved, a target sub-region is selected through an adaptive boundary to perform oversampling to balance sample data, the problem of flow imbalance of the SDN multi-access interconnection architecture is solved, meanwhile, a CNN-LSTM model fused with an attention mechanism is established, and depth feature extraction is performed on samples after the samples are balanced so as to meet dynamic features of the flow in a short sequence.

This application provides an IT device interconnection architecture and IT device, including: at least one computing power device circuit board, at least one I / O device circuit board, a first connector, and a second connector; the computing power device circuit board and the I / O device circuit board are arranged perpendicularly to each other. The computing power device circuit board is used to electrically connect to the computing power device, and the I / O device circuit board is used to electrically connect to the I / O device. By vertically arranging the computing power and I / O device circuit boards and using pluggable connections, the traditional backplane is replaced, reducing interconnection space, improving internal space utilization and component integration, achieving logic decoupling, simplifying maintenance and upgrades, and supporting speed evolution. Because the above architecture has a high aperture ratio and orthogonal layout, heat dissipation can be enhanced, allowing the use of higher power components. Furthermore, after iterating to new interface standards, no large-scale modification is required; only the corresponding circuit board needs to be replaced to adapt to future developments.

The invention discloses a hardware architecture of a multi-port memory, and belongs to the technical field of computer memory hardware circuit design. The core comprises a plurality of input ports, a plurality of output ports, a plurality of linked list FIFOs (First In First Out), an input switch internet, a plurality of block memory units, a plurality of reordering queues and an output switch internet, wherein the input port is connected with the block memory unit through the linked list FIFO and the input switch internet, and the block memory unit is connected with the output port through the output switch internet and the reordering queue. By introducing an innovative hardware architecture and a network interconnection architecture, resource consumption is effectively reduced while efficient and large-scale ports are realized, and memory access efficiency and parallel processing capability are improved; the method can be widely applied to high-performance computing, heterogeneous computing, data center acceleration and other application scenes needing high concurrent access and high throughput of a large number of ports, and stable operation of the system can be ensured under the condition of high load.

In one embodiment, an A / V interconnection architecture is provided that includes a TX A / V endpoint that supports native audio and stereo down-mixed audio on separate networks. The TX A / V endpoint outputs native audio over a video network to an RX A / V endpoint coupled to an A / V sink component that is capable of processing or outputting the native audio, and produces a stereo down-mixed version of the native audio which is output over an audio network to an audio system coupled to an audio sink component that is incapable of handling the native audio. In another embodiment, an A / V interconnection architecture is provide that enables expandable surround sound. If the number of audio channels for a type of surround sound is less than or equal to a number of local amplified output channels, surround sound is provided using only local unpowered speakers. If the number exceeds the number of the local amplified output channels, surround sound is provided using both the local unpowered speakers and one or more add on devices accessible over the audio network.

The application relates to the technical field of direct-current motor servo drive control, and provides a real-time transmission system based on a Zynq AXI4 bus and a control method thereof, wherein the system comprises a Zynq system on chip, a DDR3 public data area, an AXI4 bus interconnection architecture and a dynamic partition manager. Through implementation of the scheme, first, the multi-channel characteristics of the AXI4 bus are utilized to allocate special transmission channels for different types of data, and parallel data interaction is realized; second, the dynamic partition manager is arranged at the PL end, so that the DDR3 public data area is dynamically and real-timely divided into a plurality of partitions according to requirements, and the real-time performance of the system is improved through multi-task parallelism; third, the read-write operation of the DDR3 in each control cycle is split into a plurality of state machines through state machine precise scheduling, the state machines are combined into a state loop and are hung to the AXI4 bus, so that the key task is ensured to be completed on time, and the determinacy of the system is improved; and fourth, the size and quantity of the partitions in the DDR3 are dynamically adjusted through the dynamic partition manager, so that the storage efficiency is improved.

The invention discloses a reusable core particle interposer for the industrial control field, which is characterized in that the surface of the interposer is arranged in an asymmetrical interconnection mode and is divided into a plurality of slot areas, each slot area is allocated with a slot type, each slot area is uniformly provided with a plurality of functional areas, and each functional area can be allocated with a functional type; and an eFPGA and an interconnection channel are embedded in the interposer, the eFPGA is coupled with the interconnection channel, and the interconnection channel is arranged among a plurality of slot areas in a hierarchical interconnection mode. According to the invention, the differentiated communication requirement of the industrial control system of the master-slave architecture is met by adopting the non-peer interconnection architecture, the fragmentation customization requirement of the specific application is met by embedding the eFPGA, and the interconnection requirements of different levels with respective characteristics are met by hierarchical interconnection; and a uniform slot with a downward compatibility characteristic is designed, so that the flexibility during core particle integration is improved, and the application performance requirement and the scene adaptation requirement in the industrial control field can be met at the same time.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

This invention relates to the field of wireless communication network technology and provides a heterogeneous stream processing cluster interconnection device in a software radio system. By designing a heterogeneous computing power cluster interconnection architecture in which the radio frequency front-end layer, heterogeneous computing power pool layer, core interconnection layer, and cluster management layer work together, and with the core structure design of heterogeneous cluster internet gateway + high-speed cluster non-blocking switching + global cluster high-precision synchronization + layered cluster deployment, it breaks through the technical bottlenecks of existing heterogeneous computing power cluster integration from the hardware level, and achieves significant improvements in cluster collaboration performance, synchronization accuracy, transmission efficiency, compatibility, reliability, and engineering feasibility, effectively improving the cluster interconnection performance of the heterogeneous stream processing cluster.

The application discloses a resource scheduling method, an electronic device, a medium and a product, relates to the technical field of AI intelligent computing, and comprises the following steps: a host obtains the bandwidth utilization rate of a main switching device in a plurality of switching devices; if the bandwidth utilization rate of the main switching device is greater than a first preset utilization rate, a first cyclic query strategy is used to query whether a standby switching device that meets a preset condition exists in the remaining switching devices except the main switching device in the plurality of switching devices; if not, a target switching device that meets a preset transmission condition is determined from the plurality of first switching machines; and the target switching device is used to store to-be-computed data to a shared memory pool. By introducing a multi-level heat perception, dynamic threshold adjustment, standby path switching and cross-network data unloading mechanism in the hybrid interconnection architecture of the shared memory pool, low congestion, high throughput and high resource utilization rate under large-scale AI training and reasoning tasks are realized.

The invention discloses an interconnection architecture applied to an accelerator cluster, which can be applied to any interconnection architecture capable of prolonging a transmission distance, reducing signal loss, reducing transmission cost and power consumption and having exchange capacity, namely any architecture capable of connecting two ends in the accelerator cluster to serve as interconnection components. The characteristics of data routing and forwarding at the two connected ends are utilized, the expandability and dynamic reconfigurability of the accelerator cluster are enhanced, the resource utilization rate is improved, and the requirement of the accelerator cluster for a high-capacity switch can be directly reduced. In addition, an interconnection network deployment mode of independent networking can be achieved without using a switch, and collaborative / hybrid deployment with a traditional switch can also be achieved. In addition, the invention also has the following advantages: 1, networking is allowed under the condition that a traditional switch is not used, and the reliability and fault tolerance of the system are improved through a mode of connecting a plurality of active switching connectors in parallel; 2, on the basis of mixed use of a novel high-performance interconnection architecture and a traditional switch, the requirement of networking on high-capacity traditional switching equipment can be reduced; and 3, the expandability of the accelerator cluster is enhanced, and the system can be expanded more conveniently.

A cableless radio frequency multifunctional microsystem assembly based on a vertical interconnection architecture relates to the technical field of radio frequency signal system assembly and comprises a shell, the shell is shaped with a cooling flow channel, the shell is shaped with an inner groove, the inner groove is fixed with a cover plate, the cover plate is shaped with an upper convex cover, the inner groove of the shell is fixed with a control switching module, the control switching module is fixed with a wide and narrow band TR module, the wide and narrow band TR module is fixed with a narrow band TR module, one end of the narrow band TR module is fixed with an EW switching module, and the EW switching module is located in the upper convex cover. The radio frequency interface and the low frequency interface are vertically arranged, the traditional cable interconnection between modules is replaced, the cross-layer synchronous transmission of the radio frequency signal, the control signal and the power supply is realized, and the problem of low assembly efficiency caused by complex cable layout in plane interconnection is solved.

The invention discloses a distributed DTU plug-and-play method and system based on an Internet of Things architecture, and relates to the technical field of power distribution automation, and the method comprises the steps: configuring an IP address and an interval number in an interval unit based on a distributed data transmission unit, issuing a registration request message, carrying out the uniqueness and integrity verification through a public unit, and returning a registration result. And on the basis of successful registration, the public unit issues a device model file calling message through an MQTT message bus, analyzes a JSON format message returned by the interval unit and constructs a data table. And based on the established data table structure, the public unit issues a point table call message through an MQTT message bus, and establishes an information table for a JSON format message returned by the interval unit. And the public unit initiates TCP connection with the port according to the IP of the interval unit recorded in the information table to establish a communication channel, and performs data interrogation and control interaction operation. Intelligent operation and maintenance are realized, and the operation reliability and stability of power distribution equipment are improved.

This invention provides a satellite operating system and satellite terminal for satellite interconnection based on a unified communication protocol. The kernel layer of the satellite operating system is integrated with the communication protocol stack interpretation component, constructing a service framework consisting of a satellite-to-ground communication engine, an intra-satellite communication engine, and an inter-satellite communication engine. The satellite-to-ground remote control communication engine calls the communication protocol stack interpretation component to construct remote control structured data corresponding to remote control data according to the communication protocol. The satellite-to-ground telemetry communication engine calls the communication protocol stack interpretation component to construct telemetry data byte streams corresponding to telemetry packet data according to the communication protocol. The intra-satellite communication engine calls the communication protocol stack interpretation component to convert between intra-satellite structured data and intra-satellite data byte streams according to the communication protocol. The inter-satellite communication engine calls the communication protocol stack interpretation component to convert between inter-satellite structured data and inter-satellite data byte streams according to the communication protocol. This invention unifies the satellite-to-ground, intra-satellite, and inter-satellite communication interconnection architecture and service framework.

The application discloses a kind of based on intelligence calculation interconnection architecture computing power service decomposition method and system, the method is by receiving and analyzing service work order, matching predefined service rule to determine decomposition strategy;At the same time, real-time acquisition includes the bottom resource state of high-speed interconnection performance data, constructs global real-time resource topological atlas;Further, based on service rule and resource atlas, service target is dynamically decomposed into a series of atomic flow links and generates quantified resource demand portrait;Subsequently, using the joint optimization algorithm with the goal of minimizing total completion time, adaptively allocate computing nodes for each link, generate dynamic service execution flow chart;Finally, drive flow chart execution and monitor in whole cycle, dynamically trigger rescheduling according to performance deviation or resource change.Dynamic service execution flow chart is generated, and the joint optimization algorithm with the goal of minimizing total completion time is used to adaptively allocate computing nodes for each link, so that the real-time optimal matching between service demand and heterogeneous computing power resources is realized, and the computing efficiency and system resilience are improved.

The invention provides an FPGA interconnection architecture evaluation device based on a graph neural network, and the device comprises an input unit which is used for obtaining the description information of a target FPGA architecture and the corresponding time sequence report information; the in-block graph construction unit is used for obtaining a corresponding wiring resource graph and global features according to description information conversion; the node frequency label extraction unit is used for counting frequency information of key path nodes according to the time sequence report information; and the prediction unit is used for acquiring the accessibility and the area delay product value of the target FPGA according to the acquired wiring resource map, the global features and the frequency information of the key path nodes. The evaluation device provided in some embodiments of the disclosure can predict the accessibility and the area delay product of the interconnection architecture through the GEF model, and the calling times of a traditional evaluation tool are significantly reduced.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

The invention relates to a multi-node interconnection architecture planning and source-load balance optimization method and device and a medium, and the method comprises the steps: building a connection topology optimization model with the maximum connection effect of a photovoltaic node and a load node as a target; solving the connection topological optimization model to obtain a photovoltaic-load fixed connection scheme; on the basis of the photovoltaic-load fixed connection scheme, taking power consumption and transmission cost balance as a target to construct a power distribution optimization model; and solving the power distribution optimization model to obtain an electric quantity optimization distribution scheme. According to the invention, the problem of distributed photovoltaic absorption in a multi-node source-load imbalance scene can be solved.

The invention discloses a method and a device for improving photovoltaic consumption capability of a medium and low voltage power distribution network, and a storage medium, and belongs to the technical field of power distribution network optimization. According to the method, a cross-voltage-level collaborative interconnection architecture with a multi-terminal intelligent soft switch as a core is constructed, various resources such as distributed photovoltaic resources, energy storage resources, adjustable loads, on-load voltage regulating transformers and capacitor banks are integrated, and a multi-resource collaborative optimization model is established; constructing an uncertainty set by adopting a distributed robust optimization method to cope with photovoltaic output and load fluctuation, and solving the model through a column and constraint generation algorithm to obtain an optimal equipment configuration and operation strategy; according to the invention, the hierarchical and court barriers of a traditional power distribution network can be effectively broken, the cross-regional flexible transfer and global optimization distribution of photovoltaic power are realized, the distributed photovoltaic consumption capability is significantly improved, and the safe, stable and economic operation of the system is guaranteed at the same time.

The invention provides a resource allocation optimization method and system under a communication interconnection architecture, and belongs to the technical field of network optimization, and the method comprises the steps: recognizing and calculating a core node interaction relationship, and constructing a topological structure; performing interaction feature analysis of each node based on the topological structure, performing node aggregation by using interaction features, and constructing a plurality of calculation clusters; carrying out intra-cluster path and inter-cluster path construction on each calculation cluster; and carrying out routing strategy analysis driving by calculating the load of each calculation cluster to obtain a routing demand strategy, and carrying out communication resource allocation of intra-cluster channels and inter-cluster channels according to the routing demand strategy. The technical problems of resource waste and high communication delay caused by static resource allocation and insufficient adaptability of the communication interconnection architecture in the prior art are solved, and the technical effects of dynamically optimizing resource allocation, improving the utilization rate and reducing the delay are achieved.

The application belongs to the field of advanced packaging technology, and particularly relates to a multi-chip optical interconnection architecture and a manufacturing method. The manufacturing method comprises the following steps: S1, plating a hard mask on a substrate surface; S2, spin-coating a photoresist on the hard mask, pre-baking, aligning and exposing, developing, post-baking, transferring a lower layer circuit to the hard mask, and removing the photoresist and cleaning; S3, manufacturing a surface layer ion exchange optical waveguide; S4, printing a matrix electrode and a circuit on the substrate surface to form a controllable electric field and a lower layer optical waveguide; S5, plating a film on the substrate surface, photoetching, and etching to form an upper layer optical waveguide; S6, laying the photonic integrated chip and an arrayed waveguide grating router on the substrate surface, and aligning and coupling the photonic integrated chip and the arrayed waveguide grating router with the upper and lower layer optical waveguides; and S7, depositing a cladding layer on the substrate surface and polishing to expose the upper surface of the photonic integrated chip. The application can effectively reduce optical path intersection and improve interconnection density, thereby realizing large-bandwidth, low-loss optical interconnection between multi-chips on a chip.

The invention discloses an optical interconnection architecture, the optical interconnection architecture comprises an XPU board card, the XPU board card comprises a semiconductor chip and an optical I / O module, the optical I / O module comprises an optical driver, an optical detector array and a two-dimensional array light source, and the optical driver is electrically connected to one side of the semiconductor chip through a micro bump or direct bonding technology. The optical interconnection architecture provided by the invention has the advantages of low system complexity, short signal transmission path, low time delay and low energy consumption.

The invention relates to the technical field of distributed systems and message middleware, in particular to a cross-message middleware intercommunication system and method based on dynamic protocol conversion and quantum enhanced transaction consistency. According to the system, a cross-protocol input analysis and feature extraction unit carries out field analysis on a message node based on a protocol grammar definition; the quantum protocol conversion engine unit maps a source protocol message structure into a quantum superposition state; performing synchronous transmission through a quantum entanglement transmission channel; carrying out decoupling reconstruction on the received quantum state; the hybrid enhanced transaction coordination unit introduces a global state synchronization mechanism based on a quantum Byzantine protocol; the dynamic protocol adaptation engine unit utilizes a protocol feature analysis mechanism based on an LSTM model to carry out modeling on time sequence features in message traffic. According to the invention, high-throughput and low-delay data transmission between heterogeneous middleware is realized, and a distributed message interconnection architecture with real-time intercommunication, intelligent coordination and self-healing capabilities is constructed.

The invention discloses a system-on-chip interconnection architecture conflict optimization method based on pin multiplexing constraint. The method comprises the following steps: in a system-on-chip interconnection architecture, receiving a host access request and determining a target exchange switch group and a target slave; judging whether the target slave machine belongs to a multiplexing sensing type exchange switch group which is fixedly connected with peripheral equipment with a pin multiplexing relation in a design stage or not; if yes, querying a pin multiplexing controller to obtain a current activated peripheral identifier of the corresponding physical pin group; and based on the comparison result of the target slave identification and the currently activated peripheral identification and the busy / idle state of the exchange switch group, conflict awareness arbitration is executed, and the decision processing mode comprises immediate execution, execution permission, immediate rejection or suspension waiting. According to the method, the physical pin multiplexing constraint is fused into interconnection network hardware design and runtime arbitration, invalid access is actively prevented from the hardware level, the system resource utilization rate is improved, the software complexity is reduced, and the response certainty is enhanced.

The application discloses a 3D FPGA interconnection architecture based on a configurable repeater, which comprises a plurality of layers of dies; the vertical direction of the die comprises a post-wiring, a configurable repeater unit and a through silicon via in a silicon substrate region in sequence; the configurable repeater unit comprises an input selector, a mode selection and signal path, an output driver and a configuration memory, wherein the mode selection and signal path comprises three modes, which are a pass-through mode, a latching mode and a terminal mode. The application constructs a special low-delay data channel through a plurality of chips through the CRU pass-through mode, supports dynamic reconfiguration to adapt to traffic changes while significantly reducing transmission delay and area overhead, and can effectively absorb the reflection energy of unused branches to guarantee signal integrity, thereby providing a high-energy-efficiency and high-reliability interconnection solution for large-scale streaming data transmission.

The invention provides an inter-DIE cache consistency processing method and a data sharing acceleration device.The inter-DIE cache consistency processing method comprises the steps that an interconnection architecture of a multi-CPU DIE and a multi-IO DIE is constructed, and the limitation of strong coupling of state records and the number of DIEs in a traditional architecture is broken through in combination with a state layering state management and control mechanism. When the three-layer state data executes cache consistency maintenance, the target CPU DIE calls a local first state and a local second state, and the number of times of interaction of a cross-DIE consistency request and the data transmission amount are reduced. The third state only records the change of the cache state instead of the full-amount state, and compared with the scheme that the full-amount state needs to be stored in the prior art, the synchronization speed of dirty data in the cache to the memory can be increased, the overall transmission delay of data interaction between DIEs is remarkably reduced, the capacity requirement of a state recorder needed by upper cache consistency maintenance is reduced, and the maintenance efficiency is improved. Hardware design complexity and manufacturing cost are reduced, and system function overhead caused by invalid consistency requests is reduced.

The application relates to the technical field of GPU cluster design, in particular to a multi-GPU interconnection system, which comprises M PCIe switches and GPU chip sets corresponding to the M PCIe switches respectively, a single GPU chip set comprises N GPU chips, the GPU chips contained in the GPU chip set are connected with the corresponding PCIe switch, the nth GPU chip contained in the M GPU chip sets is connected through a preset connection relationship, the data transmission between the GPU chip sets does not need to pass through the PCIe interface between the CPU or the PCIe switch, so that the data transmission efficiency of the GPU chip interconnection architecture is guaranteed, at most, a single GPU chip needs to be connected with two other GPU chips, the wiring cost of the GPU chip interconnection is reduced, and a low-cost GPU chip can also form a GPU cluster.