69 results about "Interconnection architecture" patented technology

The invention discloses an application method and device of a switch compatible with interconnection, a storage medium and electronic equipment, and relates to the technical field of servers, and the method comprises the steps: determining the input signal level of a target port through detecting the connection state of the target port; further, under the condition that the input signal level is the first level value, it can be determined that an input and output assembly in the switch control panel is in an equipment connection mode, and a semi-interconnection architecture mode of mounting equipment can be configured for the switch; and under the condition that the input signal level is the second level value, determining that the input and output components in the switch control panel are in the switch connection mode, thereby being capable of configuring a full interconnection architecture mode for the switches, solving the technical problem of insufficient compatibility of high-speed interconnection and flexible configuration of mounting equipment between the switches, and improving the switching efficiency. The technical effects that the port configuration can be adaptively switched according to the level of the input signal, and the semi-interconnection architecture of the mounting equipment and the full interconnection architecture between the switches are compatible are achieved.

The invention belongs to the technical field of semiconductors, and discloses a multi-core GPU interconnection architecture and a self-adaptive cache allocation method thereof.The multi-core GPU interconnection architecture comprises a plurality of GPU clusters and a global cluster, the global cluster comprises a global router, a global scheduler, a directory, a memory and a plurality of GPU clusters, each GPU cluster is composed of a plurality of GPU cores, and the GPU cores are arranged in the global router. Each GPU core grain comprises a plurality of independent primary data caches, secondary data caches, a local router and a network interface, and the network interface judges whether a current request is processed by the GPU core grains in a GPU cluster or not according to whether a target address in a target node belongs to the GPU cluster or not, so that a high-level multi-core grain interconnection architecture supporting cross-cluster communication is formed. According to the method, performance is optimized by adapting to different access modes, private and shared cache modes are switched in real time, single data access delay is reduced, the overall system efficiency is improved, and the method is used for a multi-core-particle heterogeneous system with a plurality of GPUs.

The invention provides a computing device interconnection architecture and a communication method. A plurality of computing resource groups and a plurality of switches are constructed; for each computing resource group, the computing resource group comprises a plurality of computing devices which are interconnected; for different computing resource groups, the computing devices belonging to the different computing resource groups are connected through a target switch in the plurality of switches, and the target switch corresponds to the intra-group serial numbers of the computing devices; the plurality of interconnected computing devices are connected through the same interconnection communication technology, and the computing devices and the target switch are connected through the same interconnection communication technology. According to the architecture and the method provided by the invention, under the condition that the number of the devices which can be connected with the computing device is limited, the number of the devices which can be in interconnection communication with the computing device under an interconnection communication technology is greatly increased, and then on the premise that the compatibility and the communication performance are guaranteed, the implementation of larger-scale computing device networking is facilitated.

The invention provides a heterogeneous multi-core integrated chip for a robot, a controller and a control method, a heterogeneous multi-core hardware platform is realized through a chip core packaging technology, communication among cores is realized by adopting NoC Fabric, and a sensing core, a control core and an inference calculation core are connected through a network-level interconnection architecture of a hierarchical routing mechanism. Integration of perception, reasoning calculation and motion control is achieved, data transmission delay is reduced, the overall performance of a system is improved, a controller is designed based on a chip of a heterogeneous multi-core integrated architecture, efficient integration and collaborative operation of perception, calculation and control are achieved, the size of the controller is effectively reduced, and power consumption is reduced.

The invention relates to a transportation junction multi-business micro-energy network chain-type interconnection architecture, and the architecture comprises a load layer which comprises micro-energy networks of different business forms; the energy layer comprises an external energy source and a distributed power generation and energy storage system and is used for providing comprehensive energy supply for energy consumption requirements of the micro-energy grids in different commercial forms in the load layer; the energy network layer comprises different types of energy networks, the different types of energy networks carry out coupling conversion on energy of the energy layer so as to meet the energy use requirements of micro energy networks in different business states in the load layer, and coupling interaction and interconnection intercommunication between the different types of energy networks are achieved through different types of energy conversion equipment; and the cloud edge-end energy collaborative management and control system is used for regulating and controlling the energy layer, the energy network layer and the load layer by utilizing a cloud-edge-end three-layer management and control architecture so as to realize the collaboration and dynamic balance of multiple energy flows among different regions of the transportation hub.

The invention discloses a resource scheduling method, an electronic device, a medium and a product, and relates to the technical field of AI intelligent computing, and the method comprises the steps: obtaining the bandwidth utilization rate of a main switching device in a plurality of switching devices through a host, and if the bandwidth utilization rate of the main switching device is greater than a first preset utilization rate, executing the first preset utilization rate; if yes, whether standby switching equipment meeting a preset standby condition exists in the remaining switching equipment except the main switching equipment in the multiple pieces of switching equipment or not is queried based on a first circular query strategy, and if not, a target switching equipment meeting a preset transmission condition is determined from the multiple first switching equipment, the to-be-calculated data is stored in the shared memory pool through the target switch, and low congestion, high throughput and high resource utilization rate under large-scale AI training and reasoning tasks are realized by introducing multi-level popularity perception, dynamic threshold adjustment, standby path switching and cross-network data unloading mechanisms into a hybrid interconnection architecture of the shared memory pool.

The invention relates to the technical field of industrial internet, in particular to an SDN (Software Defined Network) multi-access interconnection architecture system for a complex industrial scene. Comprising a multi-access field layer module, a multi-access service flow control layer module, an SDN (Software Defined Network) exchange layer module and a unified management and control platform, an extensible protocol rule base is arranged in the multi-protocol analysis interconnection terminal, dynamic analysis and fusion of 10 + industrial protocols such as Modbus, Profinet and EtherCAT are supported, protocol islands are eliminated, hot plug updating of protocol description files is supported, and newly-added protocols do not need to be upgraded in a shutdown mode; the semantic mapping engine converts original data into standardized semantic information through a knowledge graph to realize cross-protocol data intercommunication; compared with a traditional gateway which needs to deploy independent equipment for each type of protocols, the method can process multiple protocols, the hardware cost is reduced by 60%, and the deployment efficiency is improved by three times.

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

The invention belongs to the technical field of optical fiber communication, and discloses an internal and external optical interconnection architecture of a chip. The chip internal and external optical interconnection framework comprises a printed circuit board, a glass substrate, a chip unit and an external optical interface. The glass substrate is arranged above the printed circuit board, the chip unit is arranged above the glass substrate, and the external optical interface is arranged on the side surface of the glass substrate; a rewiring layer and an optical waveguide are arranged in the glass substrate, and the rewiring layer is arranged below the chip unit; the chip unit comprises a main chip, a storage chip, an electronic integrated chip and a photonic integrated chip; the photonic integrated chip is optically coupled with an external optical interface through an optical waveguide. The invention further provides a manufacturing method of the chip internal and external optical interconnection architecture. The chip internal and external optical interconnection architecture is the chip internal and external optical interconnection architecture. According to the invention, the electrical interconnection distance of high-speed data transmission can be greatly shortened, the transmission rate and the signal quality are improved, and the device power consumption is reduced.

The invention relates to the technical field of industrial network communication, in particular to an SDN (Software Defined Network) industrial network routing method based on deep traffic classification and dynamic pheromone optimization. According to the method, an SMOTE algorithm is improved, a target sub-region is selected through an adaptive boundary to perform oversampling to balance sample data, the problem of flow imbalance of the SDN multi-access interconnection architecture is solved, meanwhile, a CNN-LSTM model fused with an attention mechanism is established, and depth feature extraction is performed on samples after the samples are balanced so as to meet dynamic features of the flow in a short sequence.

The invention provides a satellite operating system and a satellite end for realizing satellite interconnection based on a unified communication protocol, an inner kernel layer of the satellite operating system is integrated with a communication protocol stack interpretation component, and a service framework consisting of a satellite-ground communication engine, an in-satellite communication engine and an inter-satellite communication engine is constructed; the satellite-ground remote control communication engine calls a communication protocol stack interpretation component, and remote control structured data corresponding to the remote control data is constructed according to a communication protocol; the satellite-ground telemetering communication engine calls a communication protocol stack interpretation component, and constructs a telemetering data byte stream corresponding to the telemetering packet data according to a communication protocol; an in-satellite communication engine calls a communication protocol stack interpretation component, and performs conversion between in-satellite structured data and in-satellite data byte streams according to a communication protocol; and the inter-satellite communication engine calls the communication protocol stack interpretation component, and performs conversion between the inter-satellite structured data and the inter-satellite data byte stream according to the communication protocol. According to the invention, satellite-ground, in-satellite and inter-satellite communication interconnection architecture and service framework of satellites are unified.

A digital signal processor (DSP) with a global and local interconnection architecture includes a plurality of DSP hardware accelerator cores each including at least one DSP module for performing a DSP operation. The DSP further includes a global interconnect for data transfer between non-adjacent ones of the DSP hardware accelerator cores and between the DSP hardware accelerator cores and processing elements external to the DSP hardware accelerator cores. The DSP further includes a local stream interconnect associated with each of the DSP hardware accelerator cores for data transfer within each core and for data transfer between adjacent ones of the DSP hardware accelerator cores.

This application provides an IT device interconnection architecture and IT device, including: at least one computing power device circuit board, at least one I / O device circuit board, a first connector, and a second connector; the computing power device circuit board and the I / O device circuit board are arranged perpendicularly to each other. The computing power device circuit board is used to electrically connect to the computing power device, and the I / O device circuit board is used to electrically connect to the I / O device. By vertically arranging the computing power and I / O device circuit boards and using pluggable connections, the traditional backplane is replaced, reducing interconnection space, improving internal space utilization and component integration, achieving logic decoupling, simplifying maintenance and upgrades, and supporting speed evolution. Because the above architecture has a high aperture ratio and orthogonal layout, heat dissipation can be enhanced, allowing the use of higher power components. Furthermore, after iterating to new interface standards, no large-scale modification is required; only the corresponding circuit board needs to be replaced to adapt to future developments.

The invention discloses a hardware architecture of a multi-port memory, and belongs to the technical field of computer memory hardware circuit design. The core comprises a plurality of input ports, a plurality of output ports, a plurality of linked list FIFOs (First In First Out), an input switch internet, a plurality of block memory units, a plurality of reordering queues and an output switch internet, wherein the input port is connected with the block memory unit through the linked list FIFO and the input switch internet, and the block memory unit is connected with the output port through the output switch internet and the reordering queue. By introducing an innovative hardware architecture and a network interconnection architecture, resource consumption is effectively reduced while efficient and large-scale ports are realized, and memory access efficiency and parallel processing capability are improved; the method can be widely applied to high-performance computing, heterogeneous computing, data center acceleration and other application scenes needing high concurrent access and high throughput of a large number of ports, and stable operation of the system can be ensured under the condition of high load.

In one embodiment, an A / V interconnection architecture is provided that includes a TX A / V endpoint that supports native audio and stereo down-mixed audio on separate networks. The TX A / V endpoint outputs native audio over a video network to an RX A / V endpoint coupled to an A / V sink component that is capable of processing or outputting the native audio, and produces a stereo down-mixed version of the native audio which is output over an audio network to an audio system coupled to an audio sink component that is incapable of handling the native audio. In another embodiment, an A / V interconnection architecture is provide that enables expandable surround sound. If the number of audio channels for a type of surround sound is less than or equal to a number of local amplified output channels, surround sound is provided using only local unpowered speakers. If the number exceeds the number of the local amplified output channels, surround sound is provided using both the local unpowered speakers and one or more add on devices accessible over the audio network.

The invention discloses an interconnection architecture of a graphic processing chip and a simulation system. The interconnection architecture comprises the graphic processing chip and an all-optical switching chip, and the graphic processing chips are interconnected through the all-optical switching chip. According to the interconnection architecture of the graphic processing chips disclosed by the invention, networking is carried out only by utilizing the optical switching chips, so that the time delays among the graphic processing chips are consistent, and the power consumption required by the distributed all-optical switching chips is very low, so that the power consumption required by the whole architecture is relatively low.

The application relates to the technical field of direct-current motor servo drive control, and provides a real-time transmission system based on a Zynq AXI4 bus and a control method thereof, wherein the system comprises a Zynq system on chip, a DDR3 public data area, an AXI4 bus interconnection architecture and a dynamic partition manager. Through implementation of the scheme, first, the multi-channel characteristics of the AXI4 bus are utilized to allocate special transmission channels for different types of data, and parallel data interaction is realized; second, the dynamic partition manager is arranged at the PL end, so that the DDR3 public data area is dynamically and real-timely divided into a plurality of partitions according to requirements, and the real-time performance of the system is improved through multi-task parallelism; third, the read-write operation of the DDR3 in each control cycle is split into a plurality of state machines through state machine precise scheduling, the state machines are combined into a state loop and are hung to the AXI4 bus, so that the key task is ensured to be completed on time, and the determinacy of the system is improved; and fourth, the size and quantity of the partitions in the DDR3 are dynamically adjusted through the dynamic partition manager, so that the storage efficiency is improved.

The invention discloses a reusable core particle interposer for the industrial control field, which is characterized in that the surface of the interposer is arranged in an asymmetrical interconnection mode and is divided into a plurality of slot areas, each slot area is allocated with a slot type, each slot area is uniformly provided with a plurality of functional areas, and each functional area can be allocated with a functional type; and an eFPGA and an interconnection channel are embedded in the interposer, the eFPGA is coupled with the interconnection channel, and the interconnection channel is arranged among a plurality of slot areas in a hierarchical interconnection mode. According to the invention, the differentiated communication requirement of the industrial control system of the master-slave architecture is met by adopting the non-peer interconnection architecture, the fragmentation customization requirement of the specific application is met by embedding the eFPGA, and the interconnection requirements of different levels with respective characteristics are met by hierarchical interconnection; and a uniform slot with a downward compatibility characteristic is designed, so that the flexibility during core particle integration is improved, and the application performance requirement and the scene adaptation requirement in the industrial control field can be met at the same time.

The invention relates to a high-dynamic-performance micro-grid energy real-time balance control method which solves the problems that an existing micro-grid energy control method is generally poor in real-time performance and lacks high-power load impact resistance and energy real-time balance control during independent operation of a micro-grid. The method is based on a micro-grid direct-current bus interconnection architecture, adopts a master-slave and hierarchical control idea, and comprises a master-slave real-time energy control algorithm, a power feed-forward quick response algorithm and a low-delay filtering harmonic power extraction method. Unification of rapidity, reliability and stability of micro-grid energy control can be achieved, real-time balance of energy and power between complex sources and loads of the micro-grid is guaranteed, and the dynamic performance of the system is improved.

The disclosure provides an evaluation device of a FPGA interconnection architecture based on a graph neural network, which comprises: an input unit configured to obtain description information of a target FPGA architecture and corresponding timing report information; an intra-block graph construction unit configured to obtain corresponding wiring resource graphs and global features according to the description information conversion; a node frequency label extraction unit configured to obtain frequency information of critical path node occurrence according to the timing report information; and a prediction unit configured to obtain the routability and area delay product value of the target FPGA according to the obtained wiring resource graphs and global features and the frequency information of critical path node occurrence. The evaluation device provided in some embodiments of the disclosure can predict the routability and area delay product of the interconnection architecture through the GEF model, and significantly reduce the number of calls of the traditional evaluation tool.

This invention relates to the field of wireless communication network technology and provides a heterogeneous stream processing cluster interconnection device in a software radio system. By designing a heterogeneous computing power cluster interconnection architecture in which the radio frequency front-end layer, heterogeneous computing power pool layer, core interconnection layer, and cluster management layer work together, and with the core structure design of heterogeneous cluster internet gateway + high-speed cluster non-blocking switching + global cluster high-precision synchronization + layered cluster deployment, it breaks through the technical bottlenecks of existing heterogeneous computing power cluster integration from the hardware level, and achieves significant improvements in cluster collaboration performance, synchronization accuracy, transmission efficiency, compatibility, reliability, and engineering feasibility, effectively improving the cluster interconnection performance of the heterogeneous stream processing cluster.

The application discloses a resource scheduling method, an electronic device, a medium and a product, relates to the technical field of AI intelligent computing, and comprises the following steps: a host obtains the bandwidth utilization rate of a main switching device in a plurality of switching devices; if the bandwidth utilization rate of the main switching device is greater than a first preset utilization rate, a first cyclic query strategy is used to query whether a standby switching device that meets a preset condition exists in the remaining switching devices except the main switching device in the plurality of switching devices; if not, a target switching device that meets a preset transmission condition is determined from the plurality of first switching machines; and the target switching device is used to store to-be-computed data to a shared memory pool. By introducing a multi-level heat perception, dynamic threshold adjustment, standby path switching and cross-network data unloading mechanism in the hybrid interconnection architecture of the shared memory pool, low congestion, high throughput and high resource utilization rate under large-scale AI training and reasoning tasks are realized.

The invention discloses an interconnection architecture applied to an accelerator cluster, which can be applied to any interconnection architecture capable of prolonging a transmission distance, reducing signal loss, reducing transmission cost and power consumption and having exchange capacity, namely any architecture capable of connecting two ends in the accelerator cluster to serve as interconnection components. The characteristics of data routing and forwarding at the two connected ends are utilized, the expandability and dynamic reconfigurability of the accelerator cluster are enhanced, the resource utilization rate is improved, and the requirement of the accelerator cluster for a high-capacity switch can be directly reduced. In addition, an interconnection network deployment mode of independent networking can be achieved without using a switch, and collaborative / hybrid deployment with a traditional switch can also be achieved. In addition, the invention also has the following advantages: 1, networking is allowed under the condition that a traditional switch is not used, and the reliability and fault tolerance of the system are improved through a mode of connecting a plurality of active switching connectors in parallel; 2, on the basis of mixed use of a novel high-performance interconnection architecture and a traditional switch, the requirement of networking on high-capacity traditional switching equipment can be reduced; and 3, the expandability of the accelerator cluster is enhanced, and the system can be expanded more conveniently.

The invention relates to a differential pair structure, a flat differential cable and an interconnection architecture, the differential pair structure comprises a pair of conductors arranged side by side, and the pair of conductors are randomly bent in the same plane along the length direction and are arranged at equal intervals. The flat differential cable comprises at least one differential pair arranged in the same plane, an insulating layer and a shielding layer, the differential pair is of a differential pair structure, the insulating layer wraps the outer side of the differential pair to fix the differential pair, an air gap extending in the bending direction is formed between each pair of conductors, and the shielding layer is arranged on the outer side of the insulating layer. The interconnection framework comprises the flat differential cable and golden fingers which are respectively connected with two ends of the flat differential cable. According to the scheme, the differential pairs are bent at will, the transmission performance is not affected by spatial layout, air gaps are reserved between the differential pairs, and the effective dielectric constant of the insulating layer is reduced.

A cableless radio frequency multifunctional microsystem assembly based on a vertical interconnection architecture relates to the technical field of radio frequency signal system assembly and comprises a shell, the shell is shaped with a cooling flow channel, the shell is shaped with an inner groove, the inner groove is fixed with a cover plate, the cover plate is shaped with an upper convex cover, the inner groove of the shell is fixed with a control switching module, the control switching module is fixed with a wide and narrow band TR module, the wide and narrow band TR module is fixed with a narrow band TR module, one end of the narrow band TR module is fixed with an EW switching module, and the EW switching module is located in the upper convex cover. The radio frequency interface and the low frequency interface are vertically arranged, the traditional cable interconnection between modules is replaced, the cross-layer synchronous transmission of the radio frequency signal, the control signal and the power supply is realized, and the problem of low assembly efficiency caused by complex cable layout in plane interconnection is solved.

The invention discloses a distributed DTU plug-and-play method and system based on an Internet of Things architecture, and relates to the technical field of power distribution automation, and the method comprises the steps: configuring an IP address and an interval number in an interval unit based on a distributed data transmission unit, issuing a registration request message, carrying out the uniqueness and integrity verification through a public unit, and returning a registration result. And on the basis of successful registration, the public unit issues a device model file calling message through an MQTT message bus, analyzes a JSON format message returned by the interval unit and constructs a data table. And based on the established data table structure, the public unit issues a point table call message through an MQTT message bus, and establishes an information table for a JSON format message returned by the interval unit. And the public unit initiates TCP connection with the port according to the IP of the interval unit recorded in the information table to establish a communication channel, and performs data interrogation and control interaction operation. Intelligent operation and maintenance are realized, and the operation reliability and stability of power distribution equipment are improved.

This invention provides a satellite operating system and satellite terminal for satellite interconnection based on a unified communication protocol. The kernel layer of the satellite operating system is integrated with the communication protocol stack interpretation component, constructing a service framework consisting of a satellite-to-ground communication engine, an intra-satellite communication engine, and an inter-satellite communication engine. The satellite-to-ground remote control communication engine calls the communication protocol stack interpretation component to construct remote control structured data corresponding to remote control data according to the communication protocol. The satellite-to-ground telemetry communication engine calls the communication protocol stack interpretation component to construct telemetry data byte streams corresponding to telemetry packet data according to the communication protocol. The intra-satellite communication engine calls the communication protocol stack interpretation component to convert between intra-satellite structured data and intra-satellite data byte streams according to the communication protocol. The inter-satellite communication engine calls the communication protocol stack interpretation component to convert between inter-satellite structured data and inter-satellite data byte streams according to the communication protocol. This invention unifies the satellite-to-ground, intra-satellite, and inter-satellite communication interconnection architecture and service framework.

A data transmission architecture with integrated circuits is provided, comprising a clock line, a clock divider, and a first equalization circuit. The clock line is configured to transmit a clock signal at a first transmission rate from a first chip to a second chip. The clock divider is located on the second chip and is configured to receive the clock signal transmitted over the clock line and to generate and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are transmitted at a reduced transmission rate compared to the first transmission rate. The clock divider maintains current-mode logic characteristics for the divided clock signals. The first equalization circuit is configured to receive and process the divided clock signals to detect data transmitted from the first chip to the second chip.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The invention discloses a chip based on a reconfigurable neuromorphic interconnection architecture, which comprises a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS (Complementary Metal Oxide Semiconductor) reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust a routing path through a dynamic routing algorithm. The dynamic routing algorithm has the advantages that the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, so that dynamic prediction of network congestion and dynamic adjustment of a routing path are carried out, meanwhile, the CMOS switch and the memristor switch are connected in parallel, limitation of a traditional single device or static interconnection is avoided, and the network congestion can be dynamically predicted. Not only are network performance and reliability improved, but also delay and power consumption of data transmission are reduced.