Hardware interconnection architecture of reconfigurable convolutional neural network

A convolutional neural network and interconnection architecture technology, applied in the field of hardware interconnection architecture, can solve problems such as reducing resource utilization and computing performance, and achieve the effect of reducing demand

Active Publication Date: 2018-10-12
FUDAN UNIV
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Problems solved by technology

Due to the diversity of algorithms and the limitation of fixed hardware scale, when the network model changes or the type of calculation changes or the type of calculation changes, the utilization rate of resources and computing performance will be reduced.

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  • Hardware interconnection architecture of reconfigurable convolutional neural network
  • Hardware interconnection architecture of reconfigurable convolutional neural network
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[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the drawings are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. The described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments described in the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0023] The purpose of the present invention is to provide a hardware interconnection architecture of a convolutional neural network capable of reducing bandwidth requirements while improving data multiplexing capability through structural interconnection.

[0024] A hardwar...

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Abstract

The invention belongs to the technical field of hardware design of image processing algorithms, and specifically discloses hardware interconnection architecture of a reconfigurable convolutional neural network. The interconnection architecture comprises a data and parameter off-chip caching module, a basic calculation unit array module and an arithmetic logic unit calculation module, wherein the data and parameter off-chip caching module is used for caching pixel data in input to-be-processed pictures and parameters input during convolutional neural network calculation; the basic calculation unit array module is used for realizing core calculation of the convolutional neural network; and the arithmetic logic unit calculation module is used for processing calculation results of the basic calculation unit array module and accumulating a down-sampling layers, activation functions and partial sums. The basic calculation unit array module is interconnected according to a two-dimensional array manner; in a row direction, input data is shared and parallel calculation is realized by using different pieces of parameter data; and in a column direction, a calculation result is transferred rowby row to serve as input of the next row to participate in the operation. The hardware interconnection architecture is capable of reducing the bandwidth demand while enhancing the data reusing ability through structure interconnection.

Description

technical field [0001] The invention belongs to the technical field of hardware design of image processing algorithms, and in particular relates to a hardware interconnection architecture of a reconfigurable convolutional neural network. Background technique [0002] With the rise of artificial intelligence, deep learning has been widely used in computer vision, speech recognition and other big data applications, and has been more and more widely used. As an important algorithm model in deep learning, convolutional neural network has been widely used, such as in image classification, face recognition, video detection, speech recognition, etc. [0003] As the accuracy of image recognition improves, convolutional neural networks become more complex and require more computation. This makes traditional general-purpose processors with a large number of redundant resources have low performance when processing large-scale convolutional neural networks, which cannot meet the actual...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04
CPCG06N3/045
Inventor 曹伟王伶俐谢亮罗成范锡添周学功
Owner FUDAN UNIV
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