29 results about "Independent clock" patented technology

A kind of board card, cabinet, clock distribution circuit and system applied to quantum computing belong to quantum computing technical field;High-precision clock source is used to synchronize output high-speed clock signal and low-speed clock signal, ensure the synchronization of low-speed reference clock and high-speed sampling clock of multiple cabinets, multiple board cards;Independent clock distribution board card is used, high-speed clock electrical signal is converted into high-speed clock optical signal by microwave modulation light source, after optical power amplification, optical beam splitter, it is distributed to the clock distribution board card of each cabinet by optical fiber, low-speed clock electrical signal is connected to the clock distribution board card of each cabinet by radio frequency cable;High-speed clock optical signal, low-speed clock electrical signal are input to clock distribution board card, then by clock distribution board card distribution to each control board card, reduce the number of PD detector, Buffer, PLL and amplification filtering module on clock signal transmission path, reduce cabinet space use pressure and cost.

A multi-channel synchronous acquisition and transmission system based on the JESD204B protocol includes a multi-channel AD synchronous acquisition module, a signal source module, a power module and an upper computer module, wherein the signal source module sends a reference clock and multiple analog signals to the multi-channel AD synchronous acquisition module; the multi-channel AD synchronous acquisition module includes an FPGA, a multi-channel ADC, an independent clock source and multiple devices; the independent clock source receives the reference clock and transmits a sysref signal; a time window is configured in the multi-channel ADC; the FPGA generates a sync signal and synthesizes an LMFC, and an edge of the sysref signal is taken as an edge of the LMFC; in the multi-channel ADC, a corresponding ILAS is set for each digital signal; and the FPGA receives all the ILASs and digital signals, and multiple digital signals are processed synchronously.

The application relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector for establishing a control path relationship among a plurality of objects to be tested; a data bidirectional selector for establishing a data path relationship; a management component for performing independent clock gating operations on input clock trees of the plurality of objects to be tested and performing independent system reset operations on input reset signals; and a test component for coordinating the components to set the control path relationship and the data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and to perform testing. Thus, various communication protocols and interface standards can be adapted, and the requirements of chip design development and chip testing for shortening chip testing time and fast response to changes can be met.

Disclosed herein are system, method, and computer program product embodiments for adapting to malware activity on a compromised computer system by detecting timing anomalies between timing signals. An embodiment operates by analyzing first timing data accessed from a validated source and second timing data accessed from an unvalidated receiver source in order to compute a threat detection value, which is utilized to determine if there is a discrepancy or anomaly in the timing or frequency of either the validated and unvalidated sources.

This application discloses a bidirectional communication system and method for board daisy chain based on a single-wire protocol, relating to the field of computer technology. This application constructs a single-bit serial protocol daisy chain system without an independent clock line, employing dual single-wire directed links or a single half-duplex shared link to achieve bidirectional transmission between boards. This significantly reduces the hardware connection harness and input / output resource usage, lowers connector and line costs, and is suitable for scenarios involving large-scale, low-cost board cascading. After power-on, master-slave identification is automatically completed based on the upstream valid frame reception status, avoiding conflicts between multiple master nodes without the need for preset DIP switches, configuration files, or external addressing commands. The motherboard uses a preset default address, and the slave boards use an allocation method where the upstream address is incremented hop by hop, ensuring a strict correspondence between physical cascading positions and logical addresses. This achieves automatic convergence with zero manual address configuration, improving system deployment and maintenance efficiency.

The embodiment of the application provides a kind of multi-element fusion quantum time synchronization clock difference regulation method, system, equipment, the method comprises: obtaining first arrival time and second arrival time;Determine the frequency offset between first clock and second clock based on first arrival time and second arrival time, and use the frequency offset to compensate the frequency of second end;Control second end to enter locking state, initialize proportional-integral-derivative (PID) controller based on the residual error of the above frequency offset, and output phase adjustment instruction by PID controller, and the phase adjustment instruction is used to correct the bottom layer hardware parameter of second end.The above scheme can carry out high-precision synchronization of independent clock in different places at hardware level without relying on external frequency distribution.

The application discloses a ship, a ship multi-sensor positioning information synchronization method, a storage medium and a program product, structured clock signals are uniformly sent to each sensor through a reference clock device, the problem of different time references of multiple sensors caused by independent clock sources is solved from the hardware level, it is ensured that all measurement data have consistent and accurate traceable time labels, and the probability of misusing historical data due to time misalignment is reduced. In view of the inherent difference that the data update frequencies of the sensors are different, the high-frequency IMU and DVL data are intelligently matched to the low-frequency GNSS data time, fusion data with time synchronization and accurate covariance estimation are generated, and therefore the probability of interpolation error and information loss caused by inconsistent frequencies is reduced.

The invention discloses a method for improving multi-chip synchronization performance of an ADC (Analog to Digital Converter) based on an independent clock FIFO (First In First Out), aiming at the problem of difficulty in timing sequence alignment during synchronous acquisition of a multi-chip source synchronization interface ADC and an FPGA (Field Programmable Gate Array), the multi-chip synchronization performance of the ADC is improved by optimizing clock distribution and equal-length wiring design, optimizing connection logic of source synchronization interface signals in the FPGA and combining an automatic training mechanism of an ISERDES module in the FPGA. Automatic alignment of data bits is realized; and further synchronizing the data of each ADC to a unified clock domain by using a plurality of independent clock FIFOs (First In First Out). According to the invention, automatic and reliable synchronous sampling after the plurality of ADCs are powered on is realized, and the method has the advantages of high synchronization precision, strong anti-interference performance, support of multi-chip expansion, model self-adaption and the like.

The invention relates to the technical field of integrated circuits and provides a built-in self-test circuit and method for a chip. The circuit comprises a control bidirectional selector which is used for constructing a control path relation among a plurality of objects to be tested; the data bidirectional selector is used for constructing a data path relationship; the management component is used for executing independent clock gating operation on respective input clock trees of the plurality of to-be-tested objects and executing independent system reset operation on respective input reset signals of the plurality of to-be-tested objects; and the test component is used for coordinating the components so as to set a control path relationship and a data path relationship among one or more objects to be tested according to a serial relationship, a parallel relationship or a serial-parallel mixed application relationship and test. Therefore, the method is beneficial to adapting to various communication protocols and interface standards, and meets the requirements of chip design and development and chip testing for shortening the chip testing time and quickly responding to changes.

The invention provides a clock tree synthesis method related to a frequency dividing circuit. The clock tree synthesis method comprises the following steps: step 1, selectively adding / deleting buffers on a clock line; 2, dividing an independent clock region behind an output pin of a frequency dividing circuit trigger; 3, in the newly divided clock area, a clock is created again, and an independent clock network is created; step 4, adjusting clock delay by adopting an insertiondelay command, and guiding a tool to complete clock tree balance; and step 5, completing automatic wiring of the clock circuit. On the basis of the steps, the problems that time sequence violation of a frequency dividing circuit (DIV) cannot be repaired under an original clock tree synthesis method, and power consumption is increased are solved.

The invention discloses a storage chip power consumption optimization method and a storage medium, and the method comprises the steps: carrying out the independent unit division of a storage chip, obtaining a plurality of hardware modules, and enabling each hardware module to be provided with an independent clock control unit and a power supply unit; performing power consumption adjustment on the hardware module according to the idle time of each hardware module in different application scenes; wherein for any one application scene, the idle time of each hardware module is acquired to determine the level of the low-power-consumption mode to be entered by the hardware module; the low power consumption modes at least comprise a first-stage low power consumption mode, a second-stage low power consumption mode, a third-stage low power consumption mode and And according to the level of the low-power-consumption mode to be entered by the hardware module, the power consumption of the hardware module is adjusted through the clock control unit and the power supply unit. Different low-power-consumption modes are accurately matched for different application scenes, so that the power consumption is reduced to the greatest extent; and through precise control of different hardware modules, the overall performance of the storage device is not affected while low power consumption is ensured.

This invention relates to the field of firmware security detection technology, and discloses a method and system for assessing security risks of camera firmware based on the supply chain. The method includes: identifying the instruction set architecture type of heterogeneous firmware to generate an architecture annotation file list; mapping heterogeneous instructions to an intermediate representation to generate a semantic control flow graph; extracting multi-clock domain configuration parameters to generate a multi-clock domain configuration description file; performing multi-clock domain independent time acceleration simulation to acquire cross-cycle state data; analyzing the cross-cycle state cumulative difference detection time triggering conditions; and assessing the risk level of the triggering conditions to generate a risk assessment report. This invention solves the problem that existing technologies cannot detect time-triggered backdoors utilizing the independent clock domain isolation characteristics of coprocessors in heterogeneous multi-core camera firmware.

The invention provides a clock synchronization method and device, terminal equipment and a storage medium, and the method comprises the steps: carrying out the sampling through employing an independent clock, obtaining a discrete sampling signal, carrying out the cross-correlation operation, generating a frame starting point index, calculating the phase difference of two detection sub-blocks in each frame, so as to obtain a global carrier frequency offset estimation value, and carrying out the calculation of the global carrier frequency offset estimation value. Applying reverse frequency offset to the discrete sampling points to obtain a frequency offset compensation signal sequence; extracting a channel impulse response and reconstructing the channel impulse response into a continuous time waveform, taking a difference value between real peak time and the closest integer sampling point moment as sampling time offset, establishing a linear function according to the change of the offset along with a frame sequence, and performing fitting to obtain a time drift estimated value; and obtaining an original result of channel frequency response, and applying reverse phase rotation to the original result according to the time drift estimation value to obtain a channel frequency response sequence after phase correction. According to the invention, joint synchronization of detection signals in two dimensions of time and frequency can be realized on the premise of no external reference clock.

This document describes systems and techniques that enable independent clocking for configuration and status registers (CSRs). The described systems and techniques can provide a clock signal to a CSR set of an IP block with a derived clock rate an integer division slower than a clock rate of another clock signal that enables operation of the IP block, which may include communication between the IP block and an application processor. The derived clock rate is synchronous to but independent of the clock rate of the clock signal. In this way, the application processor and other entities can access the CSR set independent of clocking of the IP block. For example, the application processor can read from or write to the CSR set without waking the IP block from an Auto Clock Gated mode. By so doing, described aspects of independent clocking can reduce power dissipation associated with the CSR set.

The invention discloses a to-be-long-flat set processing method and system, a terminal and a storage medium. The method comprises the following steps: determining a clock break point according to a synchronization relationship and an asynchronous relationship in clock constraint information; generating a first to-be-prolonged flat set for the corresponding generation clock by using the clock port of each generation clock; and combining the first to-be-long-flat set corresponding to each clock break point. According to the invention, the finally obtained second to-be-prolonged flat set can accurately, completely and briefly represent the same or related synchronization relationship in the corresponding chip, and the first to-be-prolonged flat set which is not merged into the second to-be-prolonged flat set can briefly and accurately represent relatively independent clock information in the corresponding chip. The determined clock tree structure can be as simple as possible, the comprehensive information processing amount of the clock tree can be simplified under the same input condition, and the processing result and the processing time can be optimized.

The invention discloses a consistency voting method and device for multi-source time synchronization data, and relates to the technical field of high-reliability time synchronization of avionics, time sensitive networks and the like. The method comprises the following steps: respectively acquiring synchronous data including local capture time, original time deviation and cumulative frequency ratio from a plurality of independent clock sources to obtain corresponding clock source data; performing validity screening on the clock source data; extrapolating the original time deviation of each effective clock source to a set voting moment based on the cumulative frequency ratio to obtain a projection time deviation; based on all projection time deviations, determining an internally consistent credible clock source subset through bounded closure consistency verification; and according to the verification result and the redundancy condition, calculating and outputting system time correction or executing degradation output. According to the method, false deviation caused by asynchronous sampling can be eliminated, deterministic fault isolation and fault-tolerant voting are realized, and the output safety and reliability of the system in a high-safety-requirement scene are guaranteed.

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. A synchronizer flip-flop circuit (100) includes: a first latch sub-circuit (112) coupled to receive input data (101); and a second latch sub-circuit (117) coupled to the first latch sub-circuit (112). The first latch sub-circuit (112) includes: a first inverter group; a first diode connected transistor (113) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a first bias voltage to each of the inverters in the first group of inverters; and a second diode-connected transistor (114) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a second bias voltage to each of the inverters in the first group of inverters.

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

The invention provides a configurable dual-port synchronous static memory and a read-write method, and the memory comprises a storage unit which is used for storing data in a two-dimensional structure, and carrying out the independent access through a write port and a read port; the parameter configuration unit is used for receiving configuration parameters of the configuration memory, the configuration parameters at least comprise storage depth and data width, and the storage structure of the storage unit is configured according to the configuration parameters; the address decoding unit is used for automatically determining address bit width according to the storage depth, and decoding access address signals respectively received by the write port and the read port into address gating signals for accessing the storage unit; and the dual-port access unit is used for respectively controlling a write-in path of a write port and a read path of a read port based on the gating signal under the control of respective independent clocks so as to realize parallel access of different address spaces. A parameter configuration mechanism is introduced, the storage structure can be adjusted as required according to different application scenes, and the adaptability and reuse efficiency of the storage unit are improved.

This application provides a clock synchronization method and apparatus, belonging to the field of communication technology. The clock synchronization method can be applied to a first network device, which can be a network device at an intermediate node in a clock synchronization network. The method includes: switching the operating mode from a first mode to a second mode based on an acquired reset signal; the first mode is a combined mode of simultaneously operating a transparent clock mode and a normal clock mode, and the second mode is an independent mode of operating only the transparent clock mode; when the operating mode is the second mode, if a clock message is received, the clock message is forwarded. By deploying both combined and independent clock synchronization modes for the first network device, this application can ensure that when the first network device is reset, there is no need to re-establish a clock link with its third network device, thereby ensuring that its downstream network devices can continue to operate normally when the first network device is reset.

The invention discloses an industrial control cross-platform clock synchronization method based on a zero pulse and a communication link, and the method comprises the following steps: S1, confirming that a DCS system accesses a Beidou or GPS for time correction, and enabling a clock to be standard Beijing time; s2, confirming that communication data transmission between the DCS and the PLC is normal, wherein the data transmission period is between a second level and a millisecond level; s3, extracting the current clock of the system in the DCS system, and generating a timing pulse signal at the zero moment of each day through logical configuration setting; s4, the timing pulse signal is sent to the PLC through a communication link between the DCS and the PLC; s5, after the PLC receives the timing pulse signal, a clock setting function block in the PLC is triggered, and the system time of the PLC is set to be the zero moment; and S6, after time calibration is completed, the PLC continues to operate according to the independent clock until the next time calibration period. According to the method, the problem that the PLC cannot correct time under the condition that a time correction device is not added is effectively solved.

A method includes receiving a circuit design, identifying sequential elements and corresponding clocks in the circuit design, and identifying sequential elements that are not clock gated in the circuit design by running a first formal verification process on the circuit design. The method further includes modifying the circuit design to add clock gating for at least one sequential element that was identified as not being clock gated to generate a first modified circuit design.

According to the online biological water quality early warning device, a water quality sampling device is provided with an RFID tag, an electronic identity card is made for the water quality sampling device, the RFID tag and a microprocessor are provided with an independent clock chip, time service is carried out through a GPS, sampling time information and geographical position information of water are accurately stored, water sample parameters are detected by a sensor and are conditioned and transmitted to the microprocessor, and the microprocessor is connected with the water quality early warning device. The microprocessor processes and analyzes the data, stores the data in the memory, stores the data in the RFID tag through the RFID processor and the RFID reader-writer, and transmits the data to a computer or a display screen through the output interface to realize single-point water quality early warning and pollutant identification, and transmits the data to a cloud server through a wireless data network. The cloud server processes and analyzes the water quality data of multiple points and different time periods of a certain area, and water quality tracing and early warning of the certain area are achieved.

This application discloses a communication method. The method includes: a first device generates and sends a first optical signal, the first optical signal being a signal obtained by combining a first clock signal with a downlink digital signal, the first clock signal including a first transmission delay; a second clock signal being obtained by transmitting the first clock signal over a transmission link, the sum of the transmission delay of the transmission link and the first transmission delay being zero; and a second device performs time synchronization based on the second clock signal. In the technical solution of this application, the digital-analog hybrid transmission and simultaneous transmission of the clock signal and the downlink digital signal can be completed via one transmission link, and an independent clock signal transmission link does not need to be established. In addition, after transmitting the first clock signal over the transmission link, the first transmission delay in the first clock signal can be offset by the transmission delay of the transmission link, and the transmission delay of the transmission link does not need to be measured or calculated, thereby improving the accuracy of time synchronization.

The invention discloses an adaptive data sampling method based on bidirectional handshake, which comprises the following steps: receiving a first signal from a transmitting end, and feeding back a second signal to the transmitting end; the link transmission delay between the receiving end and the transmitting end is measured while the original data stream sent by the transmitting end is received, the third signal is fed back to the transmitting end, the technical problem that a single handshake protocol lacks a bidirectional dynamic coordination mechanism is solved through a three-way handshake protocol, and the reliability of data transmission is improved. Recording the number of wrong sampling times to evaluate the noise level while performing first data sampling on the original data stream; the target sampling window parameter is calculated according to the link transmission time delay, the noise level and the pre-stored dynamic calibration coefficient, the second data sampling is performed based on the target sampling window parameter, and the technical problem that the sampling position may deviate from the data bit center when the independent clock has the clock frequency is solved by dynamically adjusting the sampling window. And the bit error rate of data sampling in a noise environment is reduced.

The invention discloses a half-duplex bus communication system based on a differential signal and an independent clock, and relates to the technical field of embedded control system communication. The system aims to solve the problems of high-speed, low-delay and low-cost communication during cooperative control of multiple actuators in scenes of robots and automation equipment. The system comprises physical layer hardware, a communication protocol and a star-bus hybrid network architecture. The physical layer adopts an LVDS (Low Voltage Differential Signaling) chip to realize differential signal transmission, and five wires form a bus; the protocol realizes half-duplex communication of a multi-node shared bus through dynamic role switching, implicit token transfer and an error recovery mechanism; the star-bus hybrid architecture is combined with a first-level cache mechanism, so that the overall bandwidth and communication efficiency are improved; the system can realize a transmission rate of 100 Mbps within a distance of 1 meter, supports a bus shared by more than or equal to 8 nodes, is low in cost and easy to realize, and is suitable for a multi-actuator high-frequency cooperative control scene.

The utility model relates to a kind of time synchronization end node device based on multi-domain clock, to solve the problems such as the difficulty of multi-clock domain cooperation, insufficient redundancy reliability and cross-network synchronization bottleneck in traditional technology.The device includes double-clock domain module, supports at least two independent clock domains, each clock domain has master clock source function, and realizes the dynamic switching of master-slave relationship through synchronization interface, and supports gPTP, PTP, CAN, GNSS or ToD / PPS protocol to carry out cross-domain time synchronization;While clock source processing unit is responsible for leading out end node clock signal from multi-domain clock module, to ensure that each end node can receive accurate clock synchronization signal.The new type does not need to transform existing Ethernet switch, can realize nanosecond cross-domain time synchronization, significantly reduces deployment cost, and provides reliable time reference support for intelligent manufacturing, industrial automation and other scenarios.

An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

The invention relates to a distributed job processing system and a distributed job processing method. The distributed job processing system comprises a plurality of nodes, a distributed container node collaboration device and a shared memory, each of the plurality of nodes is provided with an independent clock, and the distributed container node collaboration device generates a job processing request according to a received task demand and issues the job processing request to the shared memory. And one or more nodes in the plurality of nodes obtain the job processing request from the shared memory and execute the job processing request. Furthermore, cooperative operation of distributed container nodes can be optimized by combining two mechanisms of random clock skew and random processing instructions.