7 results about "Independent clock" patented technology

This application discloses a bidirectional communication system and method for board daisy chain based on a single-wire protocol, relating to the field of computer technology. This application constructs a single-bit serial protocol daisy chain system without an independent clock line, employing dual single-wire directed links or a single half-duplex shared link to achieve bidirectional transmission between boards. This significantly reduces the hardware connection harness and input / output resource usage, lowers connector and line costs, and is suitable for scenarios involving large-scale, low-cost board cascading. After power-on, master-slave identification is automatically completed based on the upstream valid frame reception status, avoiding conflicts between multiple master nodes without the need for preset DIP switches, configuration files, or external addressing commands. The motherboard uses a preset default address, and the slave boards use an allocation method where the upstream address is incremented hop by hop, ensuring a strict correspondence between physical cascading positions and logical addresses. This achieves automatic convergence with zero manual address configuration, improving system deployment and maintenance efficiency.

The application discloses a ship, a ship multi-sensor positioning information synchronization method, a storage medium and a program product, structured clock signals are uniformly sent to each sensor through a reference clock device, the problem of different time references of multiple sensors caused by independent clock sources is solved from the hardware level, it is ensured that all measurement data have consistent and accurate traceable time labels, and the probability of misusing historical data due to time misalignment is reduced. In view of the inherent difference that the data update frequencies of the sensors are different, the high-frequency IMU and DVL data are intelligently matched to the low-frequency GNSS data time, fusion data with time synchronization and accurate covariance estimation are generated, and therefore the probability of interpolation error and information loss caused by inconsistent frequencies is reduced.

This invention relates to the field of firmware security detection technology, and discloses a method and system for assessing security risks of camera firmware based on the supply chain. The method includes: identifying the instruction set architecture type of heterogeneous firmware to generate an architecture annotation file list; mapping heterogeneous instructions to an intermediate representation to generate a semantic control flow graph; extracting multi-clock domain configuration parameters to generate a multi-clock domain configuration description file; performing multi-clock domain independent time acceleration simulation to acquire cross-cycle state data; analyzing the cross-cycle state cumulative difference detection time triggering conditions; and assessing the risk level of the triggering conditions to generate a risk assessment report. This invention solves the problem that existing technologies cannot detect time-triggered backdoors utilizing the independent clock domain isolation characteristics of coprocessors in heterogeneous multi-core camera firmware.

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

This application provides a clock synchronization method and apparatus, belonging to the field of communication technology. The clock synchronization method can be applied to a first network device, which can be a network device at an intermediate node in a clock synchronization network. The method includes: switching the operating mode from a first mode to a second mode based on an acquired reset signal; the first mode is a combined mode of simultaneously operating a transparent clock mode and a normal clock mode, and the second mode is an independent mode of operating only the transparent clock mode; when the operating mode is the second mode, if a clock message is received, the clock message is forwarded. By deploying both combined and independent clock synchronization modes for the first network device, this application can ensure that when the first network device is reset, there is no need to re-establish a clock link with its third network device, thereby ensuring that its downstream network devices can continue to operate normally when the first network device is reset.

The utility model relates to a kind of time synchronization end node device based on multi-domain clock, to solve the problems such as the difficulty of multi-clock domain cooperation, insufficient redundancy reliability and cross-network synchronization bottleneck in traditional technology.The device includes double-clock domain module, supports at least two independent clock domains, each clock domain has master clock source function, and realizes the dynamic switching of master-slave relationship through synchronization interface, and supports gPTP, PTP, CAN, GNSS or ToD / PPS protocol to carry out cross-domain time synchronization;While clock source processing unit is responsible for leading out end node clock signal from multi-domain clock module, to ensure that each end node can receive accurate clock synchronization signal.The new type does not need to transform existing Ethernet switch, can realize nanosecond cross-domain time synchronization, significantly reduces deployment cost, and provides reliable time reference support for intelligent manufacturing, industrial automation and other scenarios.

An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.