Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

317results about How to "Synchronization is simple" patented technology

Method and apparatus for a rearrangeably non-blocking switching matrix

A switching apparatus is disclosed that employs a relatively simple and inexpensive switching matrix, but which avoids interruption of existing connections when connections are added or removed. The switching matrix switches errorlessly by controlling the point in time at which switching occurs. Using such a technique, switching can be performed without disturbing the connections already configured in the switching matrix, and so is referred to herein as being non-blocking. Optionally, the incoming data can be rearranged to provide a larger window of time in which the switching matrix can be switched. In the case of a switch using an optical backplane, this also allows more time for various components of the system (e.g., clock/data recovery units) to re-acquire lock. The switching apparatus includes a switching matrix and control circuitry. The switching matrix has a matrix input, a control input and a number of matrix outputs, and is configured to receive an information stream at the matrix input. The information stream includes a number of portions, while the control circuitry has a control output coupled to the control input. The control circuitry is configured to initially configure the switching matrix to output the information stream at a one of the matrix outputs and to subsequently configure the switching matrix to output the information stream at another of the matrix outputs during a period of time during which the one of the portions is transiting the switching matrix.
Owner:CISCO TECH INC

Synchronizing clocks across a communication link

Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
Owner:WI LAN INC

Phase lock loop with coarse control loop having frequency lock detector and device including same

A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.
Owner:LATTICE SEMICON CORP

Synchronizing clocks across a communication link

Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
Owner:WI LAN INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products