A phase lock loop (PLL) for controlling a sampling
clock or other
clock, and a data sampling circuit,
transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-
voltage characteristic. The coarse control loop includes a frequency lock
detector and
voltage range monitoring logic. Typically, the frequency lock
detector locks operation of the coarse control loop when the difference between the VCO output
clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the
voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a
transceiver (including at least two
receiver interfaces and a
transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a
transceiver having a multi-layered
receiver interface including
digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all
layers of the
receiver interface). Each receiver
interface layer performs blind
oversampling on a different received
signal using the multiphase clock and the
digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.