40 results about "Sample rate conversion" patented technology

The invention discloses a control method and device of an audio processing system and a storage medium, and relates to the technical field of audio data processing, and the method comprises the steps: obtaining environment information and device state data collected by a sensor, and inputting the environment information and the device state data into a clock compensation module; the method comprises the following steps: generating a corresponding compensation parameter according to a preset sampling rate, performing a compensation action on an audio clock based on the compensation parameter, determining a source sampling rate corresponding to at least one audio source according to the compensated audio clock, finally detecting the source sampling rate through a sampling rate conversion module, and when the source sampling rate is different from a preset sampling rate, outputting the audio source. And adjusting the source sampling rate based on the preset sampling rate. According to the application, the audio clock is compensated, and the compensated sampling rate is uniformly converted through the sampling rate conversion module, so that clock synchronization among multi-source audio input and sampling rate unification of the multi-source audio input are realized, and the processing efficiency of the audio data is improved.

A receiver has a sample rate converter that outputs samples of orthogonal frequency division multiplexing symbols. The receiver includes a fast Fourier transform engine that receives the samples and converts them into a plurality of frequency domain sub-carriers. A timing control circuit generates a timing error and controls the sample rate converter to adjust a sample rate of the orthogonal frequency division multiplexing symbols based at least in part on the timing error.

A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

In some aspects, an audio processor (310) may provide a set of TDM clocks (330-1, 330-2) to each digital sample rate converter (325) in a time division multiplexed (TDM) data chain (320-1, 320-2), the set of TDM clocks comprising a sample rate clock input and a bit clock input. A digital sample rate converter (325) in each TDM data chain (320-1, 320-2) is connectable to respective audio ports (I2S0 to I2S7), each of which corresponds to a stereo channel. A digital sample rate converter (325) in each TDM data chain (320-1, 320-2) may receive a digital audio input via the audio ports (I2S0 to I2S7). An audio processor (310) may receive, at one or more TDM inputs (TDM (in) 0, (TDM (in) 1), a TDM audio stream from each of the one or more TDM data chains (320-1, 320-2), where the TDM audio streams mix the digital audio input based on a sample rate clock input and a bit clock input. Numerous other aspects are described.

A device for processing a digital signal includes a Farrow structure (14) that applies to the digital signal a time-varying sample rate conversion from the fixed sample rate to a time varying sampling. The digital signal sampled at the time varying sampling is a resulting signal. The Farrow structure (14) is controlled from a control variable. A spectral analysis means (15) performs a spectral analysis of the resulting signal to determine the frequency values of the resulting signal. A determining means (16) determines a sparseness parameter of the frequency values of the resulting signal. A controlling means (17) modifies the control variable according to the value of the sparseness parameter.

To provide an active noise reduction device that can shorten a delay concerning output of a correlation sound.SOLUTION: An active noise reduction device 10 includes: a first signal processor 11 that applies an adaptive filter to a reference signal having a correlation with noise in a space in a vehicle 50 to generate a cancellation signal for outputting a cancellation sound for reducing noise; a second signal processor 12 that updates a coefficient of the adaptive filter; and a sample rate converter 17. The first signal processor 11 operates in a cycle T1. The second signal processor 12 operates in a cycle T2 longer than the cycle T1. The sample rate converter 17 upsamples the coefficient of the adaptive filter updated by the second signal processor 12 for output to the first signal processor 11. The cycle T1 is longer than a difference between the maximum value and the minimum value of a processing time required until the second signal processor updates the coefficient of the adaptive filter after acquiring the reference signal.SELECTED DRAWING: Figure 1

The invention discloses a sampling rate conversion device and method and an audio playing system, in the sampling rate conversion device, a control unit determines a target filter order and a target step value based on an input sampling rate and an output sampling rate; a filter coefficient generation unit determines a target filter coefficient and a historical filter coefficient based on a multi-phase filter basic coefficient table according to sampling point address information of a target input sampling point, a target filter order and a target step value; and the multi-phase filter convolution unit performs convolution operation on the target input sample point, the target filter coefficient, the historical sample point and the historical filter coefficient based on the target filter order to obtain a target output sample point. As the order of the target filter is dynamically generated according to the input sampling rate and the output sampling rate, the filtering coefficients can be determined based on the same polyphase filter basic coefficient table for different sampling rate conversion specifications, the storage space is saved, repeated switching of the coefficient table is not needed, the conversion steps are simplified, and the conversion efficiency is improved.

The invention discloses a hearing aid and rhythm sound stimulation device based on dual-channel fusion and a control method, and the device comprises a microphone array, an analog-to-digital conversion module, a Bluetooth receiving module, an audio switching and sampling rate conversion module (ASRC), a digital signal processor (DSP), a power amplification module, and a central control unit. A Bluetooth acoustic stimulation signal injection channel is arranged between a microphone input of the hearing aid and a DSP (digital signal processor), and is divided into two paths through ASRC: one path is a Bypass Path, and a Bluetooth acoustic stimulation signal is directly output to a programmable gain amplification and amplitude limiting module and a power amplifier module; and the other path is a DSP fusion path, and the Bluetooth acoustic stimulation signal and the microphone signal are subjected to weighted fusion in the DSP. According to the hearing aid and rhythm sound stimulation device based on dual-channel fusion and the control method, a hardware-level dual-channel structure and an AI self-adaptive control algorithm are introduced into a hearing aid system, low-delay, high-fidelity and multi-mode switchable hearing compensation and nerve regulation are achieved, and the hearing aid and rhythm sound stimulation device has the low-delay (lt, 3ms), high-fidelity and multi-mode intelligent switching capacity.

The present invention discloses a method for voice sampling rate conversion. The method of the present invention includes a writing process and a reading process. The writing process is to upsample the voice signal before conversion and write it into the FIFO. The frequency F of the upsampled voice signal 2 has an error less than or equal to 0.01 with the frequency F 3 of the target voice signal. The FIFO has a write pointer, an upper warning pointer, a read pointer, and a lower warning pointer set in sequence. The reading process is that the signal receiving end reads voice data from the FIFO at the frequency F 3 . If F 3 >F 2 , when the read pointer is equal to the address value of the upper warning pointer, a random number S 1 is randomly generated. At the (S 1 +1)-th read operation, the address value of the read pointer of the FIFO remains unchanged. If F 3 <F 2 , when the read pointer is equal to the address value of the upper warning pointer, a random number S 2 is randomly generated. At the (S 2 +1)-th read operation, the address value of the read pointer of the FIFO is incremented by 2. The method of the present invention does not generate periodic jump points and repeated point operations during sampling rate conversion, improves the quality of the received voice signal, and saves the cost of the electronic system at the same time.

Methods and systems for dynamically routing pulse-code modulated (PCM) audio subchannels to one or more sink devices using a software-based router. The PCM router may set a pre-conversion buffer in the conversion path to a sink device for a particular subchannel if the source PCM fragment size differs from the sink fragment size. It may also compare characteristics of the audio subchannel to the sink device to identify a mismatch and, on that basis, configure the conversion path to include a sample rate converter, a channel converter, or a format converter, as needed. Subchannels can be dynamically routed to two or more sink devices and routing may be changed during playback.

Methods, an encoder and a decoder are configured for transition between frames with different internal sampling rates. Linear predictive (LP) filter parameters are converted from a sampling rate S1 to a sampling rate S2. A power spectrum of a LP synthesis filter is computed, at the sampling rate S1, using the LP filter parameters. The power spectrum of the LP synthesis filter is modified to convert it from the sampling rate S1 to the sampling rate S2. The modified power spectrum of the LP synthesis filter is inverse transformed to determine autocorrelations of the LP synthesis filter at the sampling rate S2. The autocorrelations are used to compute the LP filter parameters at the sampling rate S2.

The invention discloses a method for realizing asynchronous sampling rate conversion in a video signal digital-to-analog conversion process, which comprises the following steps of: designing an FIR (finite impulse response) type asynchronous sampling rate conversion filter (as shown in an attached drawing) with a frequency response function of (kT / 2) / sin (kT / 2) type; and the frequency component signal gain of the video signal subjected to digital-to-analog conversion and long-distance transmission is kept constant. Therefore, various technical indexes such as a frequency response curve, a chromaticity and brightness gain difference, group delay and a signal-to-noise ratio of video signals subjected to digital-to-analog conversion and long-distance transmission can meet requirements. The FIR type asynchronous sampling rate conversion filter is realized through an FPGA, prototype filter coefficients of 24 basic phases are stored in the FPGA, filter coefficients on finer phases and optimization of the filter coefficients are realized through 3-order Lagrange interpolation, and filtering processing of 16 paths of video signals is simultaneously realized through one FPGA module, so that the performance of the asynchronous sampling rate conversion filter is effectively improved, and the filtering efficiency is improved. And the storage space of the coefficient is saved.

A sample rate converter circuit for receiving a first signal at a first sample frequency and outputting a second signal having a second sample frequency. The sample rate converter circuit includes a rate estimator circuit structured to receive a first clock signal having the first sample frequency and a second clock signal having the second sample frequency and structured to generate an estimate of a ratio of the first sample frequency to the second sample frequency. The rate estimator circuit includes an instantaneous rate estimator circuit structured to process the first clock signal and the second clock signal to provide a noisy ratio of the first sample frequency to the second sample frequency and a low pass filter structured to filter the noisy ratio of the first sample frequency to the second sample frequency based on filter coefficients adjustable by a time constant controller of the rate estimator circuit.

A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

The present application discloses a control method, device, and storage medium for an audio processing system. The present application relates to the technical field of audio data processing. The method obtains environmental information and device status data collected by a sensor, then inputs the environmental information and the device status data into the clock compensation module to generate corresponding compensation parameters, and performs a compensation action on the audio clock based on the compensation parameters. Then, the source sampling rate corresponding to at least one audio source is determined according to the compensated audio clock. Finally, the source sampling rate is detected by the sampling rate conversion module. When the source sampling rate is different from the preset sampling rate, the source sampling rate is adjusted based on the preset sampling rate. The present application first compensates the audio clock and uniformly converts the compensated sampling rate through the sampling rate conversion module to achieve clock synchronization between multi-source audio inputs and unify the sampling rates of multi-source audio inputs, so as to improve the processing efficiency of audio data.

The invention discloses a USB audio equipment cache water level control method and device, USB audio equipment and a storage medium. A target water level value, a proportionality coefficient, an integral coefficient and a differential coefficient are preset; periodically collecting a current water level value in a buffer area of the sampling rate conversion module at a fixed sampling period; calculating a current water level deviation, a water level accumulated error and a water level error change rate according to the current water level value and a target water level value; according to the current water level deviation, the water level accumulated error and the water level error change rate, an output control value is obtained through calculation based on a PID control algorithm; amplitude limiting processing is conducted on the output control value, so that the sum of the target water level value and the output control value is within the effective capacity range of the buffer area; and dynamically adjusting the sampling rate conversion ratio of the sampling rate conversion module according to the output control value after amplitude limiting processing. A PID algorithm in the industrial control field is migrated to a digital audio stream processing scene, and high-performance audio data cache control is realized in an embedded environment.

A device (100) for shifting a digital signal (111) with a first sampling rate by a shift time to provide a shifted signal (112) with a second sampling rate, comprising: a sample rate converter (110) configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal (112), wherein the interpolated signal is based on the digital signal (111), and wherein the value of the interpolated signal is a time-shifted version of the digital signal at the second sample rate; wherein the sample rate converter is configured to modify a time interval between a sample time of the digital signal (111) and the compensated sample time based on the shift time, wherein the compensated sample time is determined based on a nominal sample time corresponding to the second sample rate and the shift time.

The invention relates to the technical field of signal processing, in particular to a sampling rate conversion device and method and electronic equipment. The sampling rate conversion device comprises a data input FIFO module, a data output FIFO module, a sampling rate conversion module and a clock control module. The data input FIFO module is used for storing data to be processed and outputting an input state signal to the sampling rate conversion module and the clock control module; the sampling rate conversion module is used for performing sampling rate conversion on the stored to-be-processed data and outputting an operation state signal to the clock control module; the data output FIFO module is used for storing the converted data after sampling rate conversion and outputting an output state signal to the sampling rate conversion module and the clock control module; and the clock control module is used for determining whether to output a clock signal to the sampling rate conversion module based on the input state signal, the operation state signal and the output state signal. According to the invention, on-demand start and stop of the clock of the sampling rate conversion module can be realized, and the low power consumption requirement of an embedded system is met.

The invention relates to the technical field of digital signal processing, and provides a signal processing method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the segmentation processing of an original digital signal according to a preset frequency domain transformation operation length and a preset overlapping coefficient, and obtaining a plurality of sub-digital signals; performing frequency domain transformation on each sub-digital signal to obtain an initial frequency domain signal corresponding to each sub-digital signal; based on the sampling rate of the original digital signal and a preset target sampling rate, carrying out sampling rate adjustment on each initial frequency domain signal to obtain a target frequency domain signal corresponding to each initial frequency domain signal; and determining a target digital signal according to the plurality of target frequency domain signals. According to the invention, the original digital signal is segmented according to the preset frequency domain conversion operation length, and only the sub-digital signal is subjected to frequency domain conversion and sampling rate adjustment each time, so that the operation amount in the conversion process is reduced, and the problem of high sampling rate conversion calculation complexity in the prior art is avoided.

The invention discloses an E-sports sound box noise reduction control method based on noise elimination and a related device, and the method comprises the steps: carrying out the audio collection processing based on a plurality of microphone devices disposed on an E-sports sound box when the E-sports sound box is applied to an online game scene; inputting the collected mixed audio signal data into a group of band-pass filters for filtering processing; performing down-sampling rate conversion processing on each frequency band audio signal data in the plurality of frequency band audio signal data; sequentially carrying out noise elimination processing on the plurality of frequency band down-sampling audio signals; performing up-sampling processing on the plurality of frequency band down-sampling audio signals after noise reduction; and recombining the plurality of frequency band up-sampling audio signals according to the same time domain to generate combined audio signal data which is noise-reduced audio data. In the embodiment of the invention, good noise reduction processing is carried out on the acquired audio signal, so that a user does not need to wear an earphone, and the user experience is improved.

A rate estimator circuit is provided for adjusting the sampling rate filter of a sampling rate converter circuit. The rate estimator circuit includes a first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency; a resolution upscaling circuit including a third integrator clocked by a system clock signal; a digital clock multiplier circuit including the second integrator and a multiplier loop circuit having a fourth integrator; a multiplier output stage connected to the output of the fourth integrator; and a rate estimator circuit including the first integrator and an estimator loop circuit having a fifth integrator.

The invention relates to an audio signal processing method and device, computer equipment and a readable storage medium, and relates to the technical field of audio processing, and the method comprises the steps: obtaining an audio signal, and determining a current sampling rate and a target sampling rate of the audio signal; determining a conversion factor sequence for the audio signal based on the current sampling rate and the target sampling rate; determining a filter type for the audio signal according to a filter constraint condition; constructing a filter identification sequence for the audio signal according to the filter type; according to the conversion factors in the conversion factor sequence, output conversion configuration is carried out on filters represented by the filter identifiers in the filter identifier sequence, and filter configuration results are obtained; based on the filter configuration result, filters at the local end are combined in sequence to obtain a filter bank, sampling rate conversion processing is carried out on the audio signals through the filter bank, and target signals conforming to the target sampling rate are obtained; therefore, the overall processing efficiency and processing precision of the audio signal can be improved.

An audio processing system (100) accepts an audio bitstream having one of a plurali-ty of predefined audio frame rates. The system comprises a front-end component (110), which receives a variable number of quantized spectral components, corresponding to one audio frame in any of the predefined audio frame rates, and performs an inverse quantization according to predetermined, frequency-dependent quantization levels. The front-end component may be agnostic of the audio frame rate. The audio processing system further comprises a frequency-domain processing stage (120) and a sample rate converter (130), which provide a reconstructed audio signal sampled at a target sampling frequency independent of the audio frame rate. By its frame-rate adaptability, the system can be configured to operate frame-synchronously in parallel with a video processing system that accepts plural video frame rates.

The application relates to a processing method and device of an audio signal, computer equipment and a readable storage medium, and relates to the technical field of audio processing. The method comprises the following steps: acquiring an audio signal, and determining a current sampling rate and a target sampling rate of the audio signal; determining a conversion factor sequence for the audio signal based on the current sampling rate and the target sampling rate; determining a filter type for the audio signal according to a filter constraint condition; constructing a filter identifier sequence for the audio signal according to the filter type; performing output conversion configuration on the filters represented by the filter identifiers in the filter identifier sequence according to the conversion factors in the conversion factor sequence, so as to obtain a filter configuration result; combining filters at a local end in sequence based on the filter configuration result to obtain a filter group, and performing sampling rate conversion processing on the audio signal through the filter group, so as to obtain a target signal conforming to the target sampling rate; and the method is beneficial to improving the overall processing efficiency and processing precision of the audio signal.

This invention discloses a high-performance cascaded integrator-comb filter with two-stage compensation. The filter includes: an N-stage conventional cascaded integrator-comb (CIC) filter module, a first compensation filter, and a second compensation filter. The N-stage CIC filter module is used to perform signal decimation or interpolation and provide basic filtering characteristics; the first compensation filter is used to compensate for the passband attenuation of the CIC filter; and the second compensation filter is used to increase the stopband zero-suppression and attenuation of the CIC filter. This invention, by cascading two simple and parameter-adjustable compensation filters, improves the passband and stopband performance of the filter while maintaining low implementation complexity, making it particularly suitable for sampling rate conversion systems with high performance requirements.

A fractional sample rate converter and phase locked loop are provided, including a first-in-first-out (FIFO) buffer, write logic, read logic, and a fractional interpolator. The write logic is configured to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and configured to generate corresponding interpolated data samples as output of the fractional sample rate converter at a second rate. The read logic is configured to transfer the input data samples in the FIFO buffer to the fractional interpolator. A ratio of the second rate to the first rate is a fraction greater than one.

The invention relates to an audio data processing system, and relates to the technical field of audio processing. The system comprises a first storage module used for storing latest-level to-be-processed data corresponding to each received to-be-processed audio data; the filter is connected with the first storage module and is used for carrying out audio sampling rate conversion processing on each level of to-be-processed data to obtain each level of sampling rate converted data corresponding to each level of to-be-processed audio data; the second storage module is respectively connected with the filter and the first storage module and is used for storing the data after sampling rate conversion at each level; the data transmission module is also used for transmitting the data after sampling rate conversion of each level to the first storage module as the Nth-level to-be-processed data corresponding to each piece of to-be-processed audio data; the sampling rate converted data of each (N-1) th-level to-be-processed data output by the filter is processed target audio data corresponding to each to-be-processed audio data; the system is beneficial to reducing the hardware overhead of audio sampling rate conversion.

An example system is configured to convert a first digital signal having a first sampling rate into a second digital signal having a second sampling rate that is different from the first sampling rate. The system includes an input circuit to receive the first digital signal at the first sampling rate; a fractional finite impulse response (FIR) circuit configured to shift the first digital signal by a value corresponding coefficients of the FIR circuit, with the value being based on an integer value or a non-integer value; memory to store the coefficients for the FIR circuit; and processing circuitry to receive information corresponding to the second sampling rate, to obtain the value based on the information, to obtain the coefficients from the memory based on the value, and to provide the coefficients to the FIR circuit.

The invention discloses a method and a system for converting audio data from a low sampling rate to a high sampling rate, and a medium. The method comprises the following steps: acquiring a digital audio signal with a low sampling rate; counting the current sampling frequency of the digital audio signal; according to the current sampling frequency and the target interpolation frequency, various interpolation parameters required by odd-even statistical fractional interpolation calculation are searched from a parameter lookup table; performing oversampling processing on the obtained digital audio signal to obtain an oversampling data sequence, and determining an interpolation coefficient according to each interpolation parameter; and reading corresponding data from the oversampling data sequence according to an odd-even crossing sequence and the interpolation coefficient, and forming a new data frame to obtain a data sequence of the digital audio signal with the high sampling rate. According to the invention, audios from different sampling rates received by the multifunctional card are unified to be output at the same rate, lossless output of converted audio signals is ensured, any frequency input can be compatible, and only a small number of logic units and storage space are used while high performance is considered.

The invention provides a multiplication-free fractional sampling rate conversion method based on multi-phase filtering, and belongs to the technical field of digital signal processing. According to the method, the fractional sampling rate conversion process based on multi-phase filtering is subjected to parallel processing, firstly, the coefficient hm (j) of each path of sub-filter is preprocessed, and I paths of multiplication-free sub-filters are designed; storing the parallel input D-path data into a shift register, and extracting the selected phase number l and the length L of a sub-filter according to multi-phase filtering to obtain I * L pieces of data to be calculated; and finally, according to the preprocessing rule of each phase of sub-filter, performing multiplication-free convolution operation on the to-be-operated data of the I sub-filters to obtain I paths of parallel output data y (m). According to the invention, the working clock of the filter is reduced, the sub-filter coefficient is preprocessed, the operation complexity is further reduced, logic resources are saved, the processing speed of the system is improved, the power consumption is reduced, and the method is suitable for high-speed transmission systems with various sampling rate conversions.