19 results about "Sample rate conversion" patented technology

In some aspects, an audio processor (310) may provide a set of TDM clocks (330-1, 330-2) to each digital sample rate converter (325) in a time division multiplexed (TDM) data chain (320-1, 320-2), the set of TDM clocks comprising a sample rate clock input and a bit clock input. A digital sample rate converter (325) in each TDM data chain (320-1, 320-2) is connectable to respective audio ports (I2S0 to I2S7), each of which corresponds to a stereo channel. A digital sample rate converter (325) in each TDM data chain (320-1, 320-2) may receive a digital audio input via the audio ports (I2S0 to I2S7). An audio processor (310) may receive, at one or more TDM inputs (TDM (in) 0, (TDM (in) 1), a TDM audio stream from each of the one or more TDM data chains (320-1, 320-2), where the TDM audio streams mix the digital audio input based on a sample rate clock input and a bit clock input. Numerous other aspects are described.

A device for processing a digital signal includes a Farrow structure (14) that applies to the digital signal a time-varying sample rate conversion from the fixed sample rate to a time varying sampling. The digital signal sampled at the time varying sampling is a resulting signal. The Farrow structure (14) is controlled from a control variable. A spectral analysis means (15) performs a spectral analysis of the resulting signal to determine the frequency values of the resulting signal. A determining means (16) determines a sparseness parameter of the frequency values of the resulting signal. A controlling means (17) modifies the control variable according to the value of the sparseness parameter.

The invention discloses a sampling rate conversion device and method and an audio playing system, in the sampling rate conversion device, a control unit determines a target filter order and a target step value based on an input sampling rate and an output sampling rate; a filter coefficient generation unit determines a target filter coefficient and a historical filter coefficient based on a multi-phase filter basic coefficient table according to sampling point address information of a target input sampling point, a target filter order and a target step value; and the multi-phase filter convolution unit performs convolution operation on the target input sample point, the target filter coefficient, the historical sample point and the historical filter coefficient based on the target filter order to obtain a target output sample point. As the order of the target filter is dynamically generated according to the input sampling rate and the output sampling rate, the filtering coefficients can be determined based on the same polyphase filter basic coefficient table for different sampling rate conversion specifications, the storage space is saved, repeated switching of the coefficient table is not needed, the conversion steps are simplified, and the conversion efficiency is improved.

The invention discloses a hearing aid and rhythm sound stimulation device based on dual-channel fusion and a control method, and the device comprises a microphone array, an analog-to-digital conversion module, a Bluetooth receiving module, an audio switching and sampling rate conversion module (ASRC), a digital signal processor (DSP), a power amplification module, and a central control unit. A Bluetooth acoustic stimulation signal injection channel is arranged between a microphone input of the hearing aid and a DSP (digital signal processor), and is divided into two paths through ASRC: one path is a Bypass Path, and a Bluetooth acoustic stimulation signal is directly output to a programmable gain amplification and amplitude limiting module and a power amplifier module; and the other path is a DSP fusion path, and the Bluetooth acoustic stimulation signal and the microphone signal are subjected to weighted fusion in the DSP. According to the hearing aid and rhythm sound stimulation device based on dual-channel fusion and the control method, a hardware-level dual-channel structure and an AI self-adaptive control algorithm are introduced into a hearing aid system, low-delay, high-fidelity and multi-mode switchable hearing compensation and nerve regulation are achieved, and the hearing aid and rhythm sound stimulation device has the low-delay (lt, 3ms), high-fidelity and multi-mode intelligent switching capacity.

Methods and systems for dynamically routing pulse-code modulated (PCM) audio subchannels to one or more sink devices using a software-based router. The PCM router may set a pre-conversion buffer in the conversion path to a sink device for a particular subchannel if the source PCM fragment size differs from the sink fragment size. It may also compare characteristics of the audio subchannel to the sink device to identify a mismatch and, on that basis, configure the conversion path to include a sample rate converter, a channel converter, or a format converter, as needed. Subchannels can be dynamically routed to two or more sink devices and routing may be changed during playback.

A sample rate converter circuit for receiving a first signal at a first sample frequency and outputting a second signal having a second sample frequency. The sample rate converter circuit includes a rate estimator circuit structured to receive a first clock signal having the first sample frequency and a second clock signal having the second sample frequency and structured to generate an estimate of a ratio of the first sample frequency to the second sample frequency. The rate estimator circuit includes an instantaneous rate estimator circuit structured to process the first clock signal and the second clock signal to provide a noisy ratio of the first sample frequency to the second sample frequency and a low pass filter structured to filter the noisy ratio of the first sample frequency to the second sample frequency based on filter coefficients adjustable by a time constant controller of the rate estimator circuit.

The invention discloses a USB audio equipment cache water level control method and device, USB audio equipment and a storage medium. A target water level value, a proportionality coefficient, an integral coefficient and a differential coefficient are preset; periodically collecting a current water level value in a buffer area of the sampling rate conversion module at a fixed sampling period; calculating a current water level deviation, a water level accumulated error and a water level error change rate according to the current water level value and a target water level value; according to the current water level deviation, the water level accumulated error and the water level error change rate, an output control value is obtained through calculation based on a PID control algorithm; amplitude limiting processing is conducted on the output control value, so that the sum of the target water level value and the output control value is within the effective capacity range of the buffer area; and dynamically adjusting the sampling rate conversion ratio of the sampling rate conversion module according to the output control value after amplitude limiting processing. A PID algorithm in the industrial control field is migrated to a digital audio stream processing scene, and high-performance audio data cache control is realized in an embedded environment.

The invention relates to the technical field of signal processing, in particular to a sampling rate conversion device and method and electronic equipment. The sampling rate conversion device comprises a data input FIFO module, a data output FIFO module, a sampling rate conversion module and a clock control module. The data input FIFO module is used for storing data to be processed and outputting an input state signal to the sampling rate conversion module and the clock control module; the sampling rate conversion module is used for performing sampling rate conversion on the stored to-be-processed data and outputting an operation state signal to the clock control module; the data output FIFO module is used for storing the converted data after sampling rate conversion and outputting an output state signal to the sampling rate conversion module and the clock control module; and the clock control module is used for determining whether to output a clock signal to the sampling rate conversion module based on the input state signal, the operation state signal and the output state signal. According to the invention, on-demand start and stop of the clock of the sampling rate conversion module can be realized, and the low power consumption requirement of an embedded system is met.

The invention relates to the technical field of digital signal processing, and provides a signal processing method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the segmentation processing of an original digital signal according to a preset frequency domain transformation operation length and a preset overlapping coefficient, and obtaining a plurality of sub-digital signals; performing frequency domain transformation on each sub-digital signal to obtain an initial frequency domain signal corresponding to each sub-digital signal; based on the sampling rate of the original digital signal and a preset target sampling rate, carrying out sampling rate adjustment on each initial frequency domain signal to obtain a target frequency domain signal corresponding to each initial frequency domain signal; and determining a target digital signal according to the plurality of target frequency domain signals. According to the invention, the original digital signal is segmented according to the preset frequency domain conversion operation length, and only the sub-digital signal is subjected to frequency domain conversion and sampling rate adjustment each time, so that the operation amount in the conversion process is reduced, and the problem of high sampling rate conversion calculation complexity in the prior art is avoided.

A rate estimator circuit is provided for adjusting the sampling rate filter of a sampling rate converter circuit. The rate estimator circuit includes a first integrator clocked by a first clock signal having a first sampling frequency and a second integrator clocked by a second clock signal having a second sampling frequency; a resolution upscaling circuit including a third integrator clocked by a system clock signal; a digital clock multiplier circuit including the second integrator and a multiplier loop circuit having a fourth integrator; a multiplier output stage connected to the output of the fourth integrator; and a rate estimator circuit including the first integrator and an estimator loop circuit having a fifth integrator.

The application relates to a processing method and device of an audio signal, computer equipment and a readable storage medium, and relates to the technical field of audio processing. The method comprises the following steps: acquiring an audio signal, and determining a current sampling rate and a target sampling rate of the audio signal; determining a conversion factor sequence for the audio signal based on the current sampling rate and the target sampling rate; determining a filter type for the audio signal according to a filter constraint condition; constructing a filter identifier sequence for the audio signal according to the filter type; performing output conversion configuration on the filters represented by the filter identifiers in the filter identifier sequence according to the conversion factors in the conversion factor sequence, so as to obtain a filter configuration result; combining filters at a local end in sequence based on the filter configuration result to obtain a filter group, and performing sampling rate conversion processing on the audio signal through the filter group, so as to obtain a target signal conforming to the target sampling rate; and the method is beneficial to improving the overall processing efficiency and processing precision of the audio signal.

This invention discloses a high-performance cascaded integrator-comb filter with two-stage compensation. The filter includes: an N-stage conventional cascaded integrator-comb (CIC) filter module, a first compensation filter, and a second compensation filter. The N-stage CIC filter module is used to perform signal decimation or interpolation and provide basic filtering characteristics; the first compensation filter is used to compensate for the passband attenuation of the CIC filter; and the second compensation filter is used to increase the stopband zero-suppression and attenuation of the CIC filter. This invention, by cascading two simple and parameter-adjustable compensation filters, improves the passband and stopband performance of the filter while maintaining low implementation complexity, making it particularly suitable for sampling rate conversion systems with high performance requirements.

A fractional sample rate converter and phase locked loop are provided, including a first-in-first-out (FIFO) buffer, write logic, read logic, and a fractional interpolator. The write logic is configured to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and configured to generate corresponding interpolated data samples as output of the fractional sample rate converter at a second rate. The read logic is configured to transfer the input data samples in the FIFO buffer to the fractional interpolator. A ratio of the second rate to the first rate is a fraction greater than one.

An example system is configured to convert a first digital signal having a first sampling rate into a second digital signal having a second sampling rate that is different from the first sampling rate. The system includes an input circuit to receive the first digital signal at the first sampling rate; a fractional finite impulse response (FIR) circuit configured to shift the first digital signal by a value corresponding coefficients of the FIR circuit, with the value being based on an integer value or a non-integer value; memory to store the coefficients for the FIR circuit; and processing circuitry to receive information corresponding to the second sampling rate, to obtain the value based on the information, to obtain the coefficients from the memory based on the value, and to provide the coefficients to the FIR circuit.

The invention discloses a method and a system for converting audio data from a low sampling rate to a high sampling rate, and a medium. The method comprises the following steps: acquiring a digital audio signal with a low sampling rate; counting the current sampling frequency of the digital audio signal; according to the current sampling frequency and the target interpolation frequency, various interpolation parameters required by odd-even statistical fractional interpolation calculation are searched from a parameter lookup table; performing oversampling processing on the obtained digital audio signal to obtain an oversampling data sequence, and determining an interpolation coefficient according to each interpolation parameter; and reading corresponding data from the oversampling data sequence according to an odd-even crossing sequence and the interpolation coefficient, and forming a new data frame to obtain a data sequence of the digital audio signal with the high sampling rate. According to the invention, audios from different sampling rates received by the multifunctional card are unified to be output at the same rate, lossless output of converted audio signals is ensured, any frequency input can be compatible, and only a small number of logic units and storage space are used while high performance is considered.

Systems and methods for asynchronous data flow in digital radios are provided. In one aspect, a demodulator circuit includes a receiver circuit configured to receive: a plurality of samples of a radio frequency signal received from a tuner, a clock, and a target size value, the receiver circuit further configured to output the samples at a first rate based on the target size value. The demodulator circuit also includes a sample rate converter configured to receive the samples from the receiver circuit and output the samples at a second rate based on a rate offset value, and a buffer configured to receive the samples from the sample rate converter and output the samples. The demodulator circuit further includes a digital demodulator configured to receive the samples from the buffer and demodulate the samples, and a control loop configured to generate the target size value.

A sampling rate converter converting input signals d(i) (i=0, 1, 2, . . . ) sampled with an input sampling rate to output signals z(j) (j=0, 1, 2, . . . ) sampled with an output sampling rate that is M / N times the input sampling rate when M / N (M and N are integers equal to or larger than 1) is set as a conversion rate includes a digital filter configured with a plurality of sub-filters arranged in poly-phase, tap coefficients being set for the sub-filters, respectively, according to the conversion rate; route selection circuitry supplies each of the input signals inputted with the input sampling rate to at least one of the sub-filters of the digital filter according to the conversion rate; and a multiplexer outputting outputs of the plurality of sub-filters as the output signals with the output sampling rate in determined order according to the conversion rate.

The application relates to a processing system of audio data and relates to the technical field of audio processing; the system comprises a first storage module used for storing latest first-level to-be-processed data corresponding to each of received to-be-processed audio data; a filter connected with the first storage module and used for performing audio sampling rate conversion processing on each level of to-be-processed data to obtain each level of sampling rate converted data corresponding to each of the to-be-processed audio data; a second storage module connected with the filter and the first storage module respectively and used for storing the sampling rate converted data; and the second storage module is further used for transmitting the sampling rate converted data to the first storage module as Nth-level to-be-processed data corresponding to each of the to-be-processed audio data; and the sampling rate converted data of each Nth-1 to-be-processed data output by the filter is target processed audio data corresponding to each of the to-be-processed audio data; and the system is beneficial to reducing hardware overhead of audio sampling rate conversion.

Control unit for a transmission system, including: a sample rate converter, which is coupled to a digital-to-analog converting unit, wherein digital input data (data_in) are feedable to the sample rate converter; a PRBS generator, wherein an output signal (ss_div) of the PRBS generator is feedable to the sample rate converter and to a delay element, wherein an output signal (ss_div_del) of the delay element is feedable to a frequency synthesizer, wherein the frequency synthesizer is clockable by a reference clock (clk_ref) and wherein an output signal (clk_ss) of the frequency synthesizer is feedable to a clock input of the sample rate converter and to a clock input of the digital-to-analog converting unit.