SSD (Solid State Disk) with multi-channel full-interconnection architecture and control method of SSD

Abstract

The invention discloses an SSD (Solid State Disk) with a multi-channel full-interconnection architecture and a control method of the SSD, which are characterized in that channels and chips are connected by utilizing a full-interconnection network, specific IDs (Identities) are distributed to different channels and chips in a routing chip through an SSD main control algorithm, different ID connections are controlled by sending commands through control pins, and the main control algorithm maintains a channel and chip state list. When a read-write request comes, the main control algorithm traverses the channels and the chip state list, finds out the channels and the chips meeting the requirements, and selects the first channel and the first chip meeting the requirements from the channels andthe chips meeting the requirements by adopting an FIFO strategy after the channels and the chips meeting the requirements exist, so that SSD solid-state disk control of a multi-channel full-interconnection architecture is realized. Interconnection between any channel and any chip is realized, and any chip and any channel do not conflict with links of other existing chips and channels after being interconnected. According to the invention, the problem of non-uniform channel utilization rate caused by conditions such as workload and the like is effectively reduced, and the read-write performanceof the SSD is improved.

Description

technical field [0001] The invention belongs to the technical field of storage, and in particular relates to an SSD solid state disk with a multi-channel fully interconnected architecture and a control method thereof. Background technique [0002] In order to meet the large-capacity and high-performance storage requirements of big data and cloud storage systems, SSD (Solid-State Drive) solid-state disks based on NAND flash have become commonly used storage media in mainstream storage systems. SSD is mainly composed of flash media and flash controller. Generally speaking, the flash controller has a structure based on an ARM processor, and the ARM processor is connected to a multi-channel NAND flash controller and a SATA / PCI-e controller through an AHB bus matrix. , The AHB bus matrix is ​​also connected with peripheral equipment, SDRAM controller, DMA controller, SRAM and ROM, etc. [0003] The connection mode of SSD internal channels and chips has undergone a transformation...

AI Technical Summary

Problems solved by technology

The following problems exist in the above channel and chip connection method. When the application load is uneven, the utilization rate of the chips belonging to different channels is different, causing some channels to be in a busy state all the time, while other channels are due to the mounted chips. The utilization rate is low and idle, so the channel utilization rate is uneven, and the read and write performance of the SSD cannot be fully utilized.

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