37results about How to "Applicable design" patented technology

The invention relates to an underground interchange bifurcate tunnel underground excavation structure which comprises at least one grade of transition segment with the section width gradually increased, a large-span tunnel maximum-section segment connected with the last grade of transition segment, a multi-arch tunnel segment, a small-distance tunnel segment and a separated tunnel segment. A reserved middle rock pillar bifurcating a tunnel is arranged between the small-distance tunnel segment and the separated tunnel segment. A middle partition bifurcating the tunnel is arranged in the middle of the multi-arch tunnel segment. One end of the bifurcated small-distance tunnel segment is connected with the multi-arch tunnel segment. One end of the bifurcated multi-arc tunnel segment is connected with the large-span tunnel maximum-section segment. The bifurcated separated tunnel segment is connected with the other end of the small-distance tunnel segment correspondingly. Compared with the prior art, according to the underground interchange bifurcate tunnel underground excavation structure, through conversion and transition of various tunnel section structures, bifurcation of the underground interchange tunnel is achieved, and the underground interchange bifurcate tunnel underground excavation structure is particular suitable for design and application of an urban underground interchange road.

A design device for designing a controller according to H infinite (H∞) logic, wherein the formula of the generalized device and the formula of the control object model as a part of the generalized device are stored in the memory unit 3; A frequency response calculation unit 4 for calculating the frequency response of the control object model and an adjustment matrix calculation unit 5 for calculating the adjustment matrix T according to the frequency response of the control object model, so that the gains of the control object model are consistent, a controller calculation unit 6, through The tuning matrix T is applied to the generalization means to calculate the parameters of a controller.

The invention relates to a variable grid internal resistance for an IGBT (Insulated Gate Bipolar Transistor) chip. The IGBT chip comprises a grid region; the grid region integrates the switching characteristic of the IGBT chip; the grid region comprises a grid pad region and a grid bus bar region; the grid internal resistance is connected in series between the grid pad region and the grid bus bar region; and the size of the grid internal resistance is between 2ohm and 10ohm. The invention also relates to a design method of the variable grid internal resistance for the IGBT chip. According to the scheme provided by the invention, the grid internal resistance is flexible and variable and has wide application range; and the defect of a fixed grid resistance value in the prior art is improved. By changing a topology of a polycrystal resistance, the regulation on the size of the polycrystal resistance can be implemented. Only by changing one mask (a polycrystal mask), the topology of the polycrystal is changed, the grid internal resistance is regulated and the variable grid internal resistance is conveniently implemented.

The invention discloses a radio-frequency power amplifier circuit with adjustable predistortion function, comprising a transistor in emitter follower structure; wherein the base electrode of the transistor is connected with the input terminal of the amplifier circuit, the emitter of the transistor is connected with the output terminal of the amplifier circuit by virtue of an output matching network, an RC parallel negative feedback network is connected between the base electrode of the transistor and the collector electrode of the transistor, a first RL series negative feedback network is connected between the collector electrode and an external adjustable bias voltage, and a second RL series negative feedback network is connected between the emitter of the transistor and the ground. Predistortion circuit can be caused to have better accuracy, gain compression and positive phase deviation produced by power amplifier post-stage circuit can be compensated, and linearity thereof can be improved.

The invention discloses an image processing-oriented reconfigurable architecture platform design method. The design method first analyzes and summarizes the various operation types of commonly used complex algorithms. Secondly, the image algorithm processing flow is divided into software and hardware under the reconfigurable architecture. Then, the reconfigurable unit design and implementation of multi-type image algorithm operation types are carried out, and on this basis, the scheme design and technical implementation of the general complex algorithm global interconnection architecture are carried out. Finally, based on this architecture, the design and implementation of a general convolution operation IP core is carried out.

The invention relates to a Nand Flash parameter reading method. The method includes the following steps that a Nand Flash reading command is sent, and a first section of Nand Flash parameters in multiple sections of Nand Flash parameters are read, wherein each section of Nand Flash parameters includes a first part of data and a second part of data; the first part of data are verified for the first time, and if verified to be corrected in the first time of verification, the first part of data continue to be verified for the second time; if the first part of data are verified to be corrected in the second time of verification, values of parameters in the first part of data are compared with values set by a program; if the values of the parameters in the first part of data and the values set by the program are the same, it is determined that Nand Flash parameter reading succeeds. Through the method, automatic identification of Nand Flash parameters is achieved without adding memorizers or increasing cost.