Highly reliable network server system on chip and design method thereof

Abstract

The invention discloses an on-chip network router system with high reliability and a design method thereof, wherein, the design method of the on-chip network router system with high reliability comprises the steps that: a router soft core based on a wormhole routing swap mode and a rotation routing selection mode is designed; a corresponding SCAC coding circuit, an SCAC decoding circuit and an SCAC error correction circuit are designed for data with a specified width; and the SCAC error correction circuit is added into the router; the SCAC coding circuit and the SCAC decoding circuit are connected with the router so as to from a framework of the router system; an SCAC-TMR fault tolerance proposal is designed for the framework of the router system and the on-chip network router system with high reliability is realized; the functions of the on-chip network router system with high reliability are tested and verified and the performance of the on-chip network router system with high reliability is evaluated. The on-chip network router system with high reliability of the invention can reduce the area, the energy consumption and the expenses of the on-chip network, ensure the reliable data transmission of the on-chip network and prevent a signal jumping with a relatively long time delay from appearing on the channel, thus being more applicable to the design of fault-tolerant and multi-core processors in the future.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, and is mainly aimed at a design method of an on-chip network, in particular to a highly reliable on-chip network router system and a design method thereof. Background technique [0002] At present, in nanotechnology and multi-core processors, on-chip interconnect lines have become a key bottleneck restricting performance and power consumption requirements in chip design. To this end, the researchers designed an on-chip communication network based on packet transmission, also known as Network-on-Chip (NOC), to meet the requirements of system performance and power consumption, and it is suitable for multi-core processors. However, VLSI systems suffer from severe loss of signal integrity due to the presence of parasitic elements in the circuit, such as time delays caused by crosstalk, which is common on long interconnect lines. At the same time, due to external radiation or electri...

AI Technical Summary

Problems solved by technology

Adopting this scheme needs to add two additional asynchronous clocks or a higher-frequency master clock to the integrated circuit, which is unacceptable for integrated circuit design

At the same time, the effect of crosstalk is more significant in high-speed devices, and the time delay caused by crosstalk in these devices is likely to exceed the maximum sampling interval of the system, that is, the wrong data is sampled twice

Therefore, there will be problems when this scheme is applied to high-speed circuits

Finally, TS needs to be sampled three times in one cycle, and its voting circuit flips three times in one cycle, which brings additional power consumption

[0005] With the improvement of integrated circuit frequency and technology, the delay caused by crosstalk on the bus is increasing, and may even exceed the clock cycle

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