This invention relates to the field of
network communication technology, specifically to a flow control optimization
algorithm for an FPGA-based intelligent conferencing
system. It constructs a central
control unit (CCU) with the FPGA as its core, and uses a cascaded
CAM to segment the 48-bit
MAC address into six 8-bit sub-keys for parallel searching, outputting the matching result in one
clock cycle. A
system cycle of 1-5ms is set, and data is transmitted in time slots according to the order of SOC frames, real-
time data frames, SOA frames, non-real-
time data frames, and
TAIL frames, isolating real-time and non-real-
time data. A dynamically maintained
MAC address table based on an aging mechanism is established to achieve adaptive topology changes for slave devices. Dynamic priority
polling arbitration is used to fairly allocate shared storage resources across multiple
PHY interfaces. This invention achieves zero-conflict, high-
bandwidth utilization network data transmission at a rate of 1000Mbit / s, significantly reducing FPGA
resource consumption, improving the real-time performance and reliability of the conferencing
system, and is suitable for multi-slave distributed intelligent conferencing scenarios.