113 results about "Scan circuits" patented technology

A display substrate is provided. The display substrate includes a display substrate, comprising one or more scan circuits and one or more electrostatic discharge protection circuits in a peripheral area. An electrostatic discharge protection circuit is configured to provide a start signal to a scan unit of a scan circuit. The display substrate comprises a plurality of islands and a plurality of bridges connecting the plurality of islands in the peripheral area; a respective island of the plurality of islands comprises at least one scan unit of the scan circuit; and one or more signal lines connecting the electrostatic discharge protection circuit and the scan unit is at least partially in an individual bridge connecting the electrostatic discharge protection circuit and the scan unit.

The embodiment of the invention provides a display device and a display panel, relates to the technical field of display, and is used for improving the display effect of the display panel. The display device includes a control circuit and a display panel. The control circuit outputs a first control signal when the refresh frequency of the display device is a first frequency, or outputs a second control signal when the refresh frequency of the display device is a second frequency. The first frequency is greater than the second frequency. The display panel comprises a plurality of scanning circuits and a plurality of rows of sub-pixels, and each scanning circuit is connected with at least one row of sub-pixels. The scanning circuit outputs a first scanning signal according to the first control signal, or outputs a second scanning signal according to the second control signal. Wherein the signal parameter of the first scanning signal is different from the signal parameter of the second scanning signal, so that the brightness difference when the display panel displays the set gray scale at the first frequency and the second frequency is within a preset range.

The invention discloses a circuit board testing and quality screening automation method and system, and aims to solve the problems of low efficiency, insufficient precision and imperfect quality control of traditional circuit board testing. Precise positioning of the circuit board is achieved through the high-precision X / Y / Z three-dimensional positioning mechanical arm, parallel testing is conducted in combination with equipment such as a multi-channel oscilloscope, a signal source and a spectrum analyzer, and the testing efficiency is improved. Temperature and humidity control testing is carried out through the environment simulation bin, the thermal imager scans temperature distribution of the circuit board, a high-precision instrument is used for detecting signal integrity and analyzing electromagnetic compatibility, and the performance of the high-speed circuit board is ensured. A machine learning algorithm predicts potential faults, a test process is optimized, an automatic sorting system is adopted to separate qualified and unqualified circuit boards, and high consistency and high reliability of product quality are ensured. Through the automatic and intelligent testing process, the production efficiency, the quality control capability and the testing precision are greatly improved, and the labor cost and the production risk are reduced.

The invention relates to a fluxgate zero flux abnormal state detection and recovery circuit and method. The fluxgate zero flux abnormal state detection and recovery circuit comprises a fluxgate probe, a feedback control circuit, a signal sampling and processing circuit, a selection circuit, a scanning circuit or a digital control and processing module. The scanning circuit and the digital control and processing module can periodically scan a compensation current amplitude from small to large, generate a periodic compensation current waveform, forcibly excite a magnetic core to exit a magnetic saturation region so as to recover a zero magnetic flux state, capture a signal of the compensation current in time, and keep normal work when the current suddenly changes or is saturated and does not work. Switching the compensation current control right of the feedback winding from a feedback signal of a feedback control circuit to a scanning signal when it is judged that the feedback winding is in the zero magnetic flux abnormal state; and when it is detected that the excitation magnetic core recovers to the zero magnetic flux state, the compensation current control right is switched from the scanning signal to the feedback signal. The reliability of the fluxgate sensor can be improved.

The present disclosure provides a scanning device and a scanning method of a touch screen, and relates to the field of display. The scanning device comprises an odd scanning circuit, an even scanning circuit and a touch position determination circuit. The odd scanning circuit comprises a plurality of odd scanning channels formed by a plurality of receiving electrodes in a manner of adjacent two-by-two groups. The odd scanning circuit obtains the sum of sensing signals from two receiving electrodes in the odd scanning channel as an odd scanning signal from the odd scanning channel. The even scanning circuit comprises a plurality of even scanning channels formed by a plurality of receiving electrodes in a manner of adjacent two-by-two groups. The even scanning circuit obtains the sum of sensing signals from two receiving electrodes in the even scanning channel as an even scanning signal from the even scanning channel. The touch position determination circuit determines a touch detection result based on a plurality of odd scanning signals obtained from a plurality of odd scanning channels and a plurality of even scanning signals obtained from a plurality of even scanning channels, so as to improve the accuracy of the touch detection result.

A scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor; and a first connecting line connecting a gate electrode of the seventh transistor to a second clock signal line; and a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both a first capacitor electrode and the second capacitor electrode of the first capacitor. An orthographic projection of the first connecting line on a base substrate at least partially overlaps with an orthographic projection of the sixth connecting line on the base substrate.

This document describes apparatuses and techniques for an interleaved scan architecture for concurrent testing of integrated circuit (IC) chips. In various aspects, an IC or system-on-chip may include interleaved scan circuitry, IP blocks or functional blocks on independent power rails, block selection logic, and a scan out combiner. The interleaved scan circuitry can receive test signaling that includes a set of test input / outputs (I / Os) at a first clock rate and generate, based on the received test signaling, multiple sets of test I / Os at a second clock rate for distribution to respective ones of the blocks. In some aspects, the second clock rate is lower than the first clock rate, which enables relaxing of timing constraints during testing and avoids usage of costly test-specific timing buffers. As such, the described aspects can reduce chip test time and reduce silicon complexity by avoiding the need for test-specific timing or power circuitry.

A scan circuit applicable to driving a plurality of light-emitting-diodes of a plurality of scan lines of a display panel is provided. A plurality of switching components are configured, having each switching component connected with one of the scan lines. A plurality of power transistors are disposed corresponding to the scan lines, having each power transistor connected between one scan line and a ground terminal. A low-dropout regulator circuit or a global operational amplifier is alternatively connected to the plurality of switching components in common for selectively generating an output voltage to at least one of the scan lines and avoiding ghost imaging on the display panel. By employing the proposed scan circuit, the invention is effective in achieving de-ghost functioning and avoiding conventional signal coupling issues on the display panel. In addition, redundant power waste consumption can be significantly reduced at the same time.

The scanning circuit includes: a first clock signal line (CKL); a second clock signal line (CBL); and a first scanning unit (SU1), a first dummy scanning unit (DSU1), and a second scanning unit (SU2), the first scanning unit (SU1), the first dummy scanning unit (DSU1), and the second scanning unit (SU2) being sequentially arranged in a region including the plurality of scanning units and the one or more dummy scanning units (DSU). Each scanning unit includes a first pad (PAD1) and a second pad (PAD2). The first pad (PAD1) includes a gate (G7) of the seventh transistor (T7). The second pad (PAD2) includes a gate (G1) of the first transistor (T1) and a gate (G3) of the third transistor (T3). The first dummy scanning unit (DSU1) includes a first dummy extension (DE1). A first dummy extension (DE1) is connected to a second pad (PAD2) in the second scan cell (SU2), and is configured to transfer one of the first clock signal (CK) or the second clock signal (CB) to a gate (G1) of the first transistor (T1) and a gate (G3) of the third transistor (T3) in the second scan cell (SU2).

To improve image quality in a solid-state imaging element that simultaneously performs exposure in all pixels.The solid-state imaging element includes a predetermined number of capacitive elements, a pre-stage circuit, a selection circuit, a post-stage circuit, and a vertical scanning circuit. The pre-stage circuit generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes each of the capacitive elements to hold a corresponding one of the reset level and the signal level. In the selection circuit, a selection transistor that opens and closes a path between one end of each capacitive element and a predetermined node is arranged. The post-stage circuit sequentially reads the reset level and the signal level via the node. The vertical scanning circuit performs control to lower the potential of the one end when the reset level and the signal level are held.

A scanning display with short-circuit detection function and a scanning device thereof, comprising: a display device including a common-cathode light-emitting diode array and including multiple scan lines and multiple data lines; and a scanning device including multiple scanning circuits. Each scanning circuit includes a voltage generator and a detector. The voltage generator has an output terminal electrically connected to a corresponding scan line and is controlled to generate one of a reference voltage and a clamping voltage to the corresponding scan line. The detector detects the voltage at the output terminal of the voltage generator and generates a detection result indicating whether the corresponding scan line is abnormal based on the voltage at the output terminal and a detection timing signal.

A scanning circuit having multiple stages is provided. Each stage of the scanning circuit includes a respective scanning unit configured to provide a control signal to at least one row of sub-pixels. Each scanning unit includes an input sub-circuit configured to receive a start signal or an output signal from a previous scanning unit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit. The output sub-circuit includes a first output transistor. The input sub-circuit includes a first input transistor and a second input transistor coupled in series between an input terminal and a first node. The first node is coupled to a gate of the first output transistor. The first processing sub-circuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

Discussed is a driving module including a PCB having a plurality of circuit printed layers, a plurality of driver ICs attached to the PCB to transmit at least one signal, a plurality of scan ICs attached to the PCB in a manner of being located at positions different from those of a plurality of the driver ICs, a driver circuit connecting a first driver IC and a second driver IC among a plurality of the driver ICs together in a first direction, a scan circuit connecting a first scan IC and a second scan IC among a plurality of the scan ICs together in the first direction, and a controller controlling at least one of a plurality of the driver ICs, a plurality of the scan ICs, the driver circuit, or the scan circuit.

A scan circuit is provided. The scan circuit includes a plurality of scan units. A respective scan unit of the plurality of scan units includes a plurality of transistors. A respective gate electrode of a respective transistor of the plurality of transistors includes a first portion and a second portion in different layers. First portions of respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with a power supply signal. Second portions of the respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with gate scanning signals, respectively. First portions of gate electrodes of at least two transistors in the respective scan unit are parts of a unitary structure.

In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

The application provides a token ring-based spike scanning arbitration circuit, which comprises a spike scanning circuit and a token ring circuit; the spike scanning circuit comprises a first complementing unit, a preprocessing unit composed of a subtraction unit and an inverter INV connected in sequence, and an AND gate AGND and an OR gate OR; and the token ring circuit comprises an edge detection unit, a token unit and a second complementing unit connected in sequence. The token ring circuit can use tokens to fairly distribute priorities among all request signals, the spike scanning circuit scans the request signals, and outputs corresponding response signals according to the priorities of the request signals, so that the speed of the arbitration circuit is improved, the fair arbitration in time and space is realized, and the imaging quality of a dynamic visual sensor is effectively improved.

To prevent a reduction in display quality in a display that writes signals in a plurality of pixels.SOLUTION: A display has: a display area including a plurality of pixels arranged in a matrix, the pixels each including a writing control transistor, a light emission control transistor, and a driving transistor driving a light emitting device; first selection lines connected to the writing control transistors in the pixels arranged in a row direction; second selection lines connected to the light emission control transistors in the pixels arranged in the row direction; a first scan circuit that sequentially scans the plurality of first selection lines; and a second scan circuit that scans the plurality of second selection lines. Image data is divided into a plurality of regions different in resolution, and the plurality of regions are arranged so that at least two or more regions are included in a column direction. The speed of scanning performed by the first scan circuit is different in each of the regions arranged in the column direction. The speed of scanning performed by the second scan circuit is equal to or more than the minimum speed and less than the maximum speed of scanning performed by the first scan circuit.SELECTED DRAWING: Figure 1

A scan circuit is provided. The scan circuit includes a plurality of scan units. A respective scan unit of the plurality of scan units includes a plurality of transistors. A respective gate electrode of a respective transistor of the plurality of transistors includes a first portion and a second portion in different layers. First portions of respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with a power supply signal. Second portions of the respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with gate scanning signals, respectively. First portions of gate electrodes of at least two transistors in the respective scan unit are parts of a unitary structure.

The invention provides a display driving circuit, a display panel and an intelligent terminal, the display driving circuit comprises a grid electrode scanning circuit and a source electrode driving circuit, when an Mth frame of image is displayed, the grid electrode scanning circuit is used for controlling a (2i-1) th row of pixel units and a 2i-th row of pixel units to synchronously start scanning, the source driving circuit is used for writing the image data of the (2i-1) th row in the Mth frame into the (2i-1) th row of pixel units and the (2i) th row of pixel units which start scanning synchronously; when an (M + 1) th frame of image is displayed, the grid electrode scanning circuit is used for controlling the 2i-th row of pixel units and the (2i + 1) th row of pixel units to synchronously start scanning, and the source electrode driving circuit is used for writing image data of the 2i-th row in the (M + 1) th frame into the 2i-th row of pixel units and the (2i + 1) th row of pixel units which synchronously start scanning. According to the display driving circuit provided by the invention, the display refresh rate can be improved, inter-line image information position compensation can be provided, and related problems such as image edge and oblique line information display sawteeth can be improved.

A display device includes a display panel and a scan circuit configured to provide control signals to the display panel. A plurality of scan units are grouped into N groups, N being a positive integer greater than 2. Each scan unit group includes one or more scan units. The scan circuit further includes N control units respectively connected to the N scan unit groups, and N selection units connected to the N control units. Each control unit of the N control units is configured to provide a start signal to a respective scan unit group of the N scan unit groups. Each selection unit of the N selection units is configured to transmit one or more selection signals to a respective control unit.

The present invention discloses a scanning circuit and a display panel. The scanning circuit includes: a driving control module, a first output module, and a second output module. The driving control module is used to control the potential of the first node and the second node according to a trigger input signal, a first clock signal, a second clock signal, and a first potential signal; the first output module is used to output a third clock signal in response to the potential of the first node, or to output a first potential signal in response to the potential of the second node; the second output module is used to output the first clock signal in response to the potential of the first node, or to output the first potential signal in response to the potential of the second node; wherein the waveforms of the first clock signal and the second clock signal are the same and the pulses do not overlap, the pulse width of the first clock signal is greater than the pulse width of the third clock signal; and the pulse time of the third clock signal is within the pulse time of the first clock signal. The present invention is conducive to the realization of a narrow bezel of a display panel.

A scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor; and an input subcircuit including a first transistor, and an input signal line configured to provide an input signal to the first transistor. The respective stage of the scan circuit further includes a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both the first capacitor electrode and the second capacitor electrode of the first capacitor. A shortest distance between an active layer of the seventh transistor and the input signal line is less than a shortest distance between an active layer of the sixth transistor and the input signal line.

Embodiments of the present disclosure relate to scan circuits and methods. In one embodiment, a method of performing a scan includes entering a scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and de-asserting a scan enable signal to perform a shift and a capture operation, respectively, on the first scan chain; controlling a further scan flip-flop with the first scan chain while applying the test pattern through the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect a fault.

A display substrate includes a scan circuit, a first reference signal line in a third region, and at least three clock signal lines arranged in a fourth region. The scan circuit includes a plurality of stages, wherein a respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node.

To provide a photoelectric conversion device capable of reducing the influence of noise caused by a global electronic shutter operation.SOLUTION: A solid-state imaging device includes a pixel array in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, and a scanning circuit that performs scanning for sequentially selecting a row from the plurality of rows in which the pixels output signals, wherein a first pixel arranged in a first region of the pixel array outputs a signal based on incident light, and a second pixel arranged in a second region of the pixel array does not output a signal based on incident light. A reset operation starts or ends in a period in which pixels in one row of the pixel array output signals, and the number of times of the reset operation performed in the second pixel is larger than the number of times of the reset operation performed in the first pixel in a period from the start of one scanning to the start of the next scanning.SELECTED DRAWING: Figure 6

The invention discloses a circuit board offset detection method, a circuit board offset detection system, equipment and a medium, and the circuit board offset detection method comprises the steps: scanning a circuit board in a first scanning direction to obtain the position and contour of a detection mark on each layer of substrate of the circuit board, and generating a first detection pattern; splicing the first detection pattern of each layer of substrate to generate a first spliced pattern; acquiring a first preset detection pattern; and judging whether the first spliced pattern is consistent with the first preset detection pattern or not, and determining whether the substrates deviate or not during stacking. Therefore, by comparing the first splicing pattern with the first preset detection pattern, whether the multiple layers of substrates deviate or not during stacking is judged, a worker can select a processing mode of the circuit board according to a detection result, and whether the substrates of the circuit board deviate or not can be determined by using the circuit board deviation detection method before processing such as drilling of the circuit board. Therefore, the cutter can be prevented from machining the circuit board with the substrate deviating as much as possible, and defective products of the circuit board can be reduced.

The present invention relates to an electronic paper panel architecture, comprising a display panel, a source driver chip for driving the display panel, and a plurality of scan lines. In addition, it also comprises a gate row scanning circuit for driving the plurality of scan lines. The gate row scanning circuit comprises a plurality of driving units, each driving unit is provided with an input end, a first output end, and a second output end. Each input end is electrically connected to a clock signal pin in the source driver chip, each first output end is electrically connected to a scan line, the second output end in the first driving unit is electrically connected to the start signal pin in the source driver chip, the first output end in the last driving unit is also electrically connected to the end signal pin in the source driver chip, and the first output ends in all driving units except the last are also electrically connected to the second output end in the next driving unit. The present invention solves the technical problem of needing to adopt multiple scan line driving circuits, thereby reducing the module manufacturing cost.

An array substrate having a display area and a peripheral area is provided. The array substrate comprises a plurality of pixel driving circuits located in a display area; the grid signal driving circuit is positioned in the peripheral area; a source integrated circuit located in the peripheral area; and a scanning circuit located in the peripheral area. Each of the plurality of pixel driving circuits includes a second transistor and a ninth transistor coupled between the first node and the third node. A gate of the ninth transistor is coupled to a third gate line. A gate of the second transistor is coupled to a second gate line. The orthographic projection of the second grid line on the substrate is at least partially overlapped with the orthographic projection of the third grid line on the substrate.

A scan circuit is provided. The scan circuit includes a plurality of scan units cascaded. A respective scan unit of the plurality of scan units includes a first subcircuit connected to a first node; a second subcircuit connected to the first node and a second node; a third subcircuit connected to the second node and a third node; a fourth subcircuit connected to a fourth node and a sixth node; and a fifth subcircuit configured to output an output signal through an output terminal, and is connected to the fourth node. The first subcircuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor. A gate electrode of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. A first electrode of the thirteenth transistor is configured to receive an input signal from an input terminal.

The invention relates to the technical field of chip testing, in particular to a chip scanning circuit, which comprises a scanning mode selection signal, P first scanning units {q1, q2,..., qp,..., qP}, S second scanning units {r1, r2,..., rs,..., rS}, a second interface, a third interface, a fourth interface, a fifth interface, a first selector and a second selector, the first selector comprises a first enabling end, a first selection input port, a second selection input port and a first selection output port, and the second selector comprises a second enabling end, a third selection input port, a fourth selection input port and a second selection output port. Therefore, the connection mode of the scanning chain can be correspondingly switched by switching the level of the scanning mode selection signal, so that a full scanning mode and a compression scanning mode are adapted, the flexibility of a scanning test is greatly improved, and complex test requirements can be met.