The invention relates to the technical field of
chip testing, in particular to a
chip scanning circuit, which comprises a scanning
mode selection signal, P first scanning units {q1, q2,..., qp,..., qP}, S second scanning units {r1, r2,..., rs,..., rS}, a second interface, a third interface, a fourth interface, a fifth interface, a first selector and a second selector, the first selector comprises a first enabling end, a first selection input port, a second selection input port and a first selection output port, and the second selector comprises a second enabling end, a third selection input port, a fourth selection input port and a second selection output port. Therefore, the connection mode of the scanning chain can be correspondingly switched by switching the level of the scanning
mode selection signal, so that a full scanning mode and a compression scanning mode are adapted, the flexibility of a scanning test is greatly improved, and complex
test requirements can be met.