12 results about "Scan circuits" patented technology

A scanning circuit having multiple stages is provided. Each stage of the scanning circuit includes a respective scanning unit configured to provide a control signal to at least one row of sub-pixels. Each scanning unit includes an input sub-circuit configured to receive a start signal or an output signal from a previous scanning unit, a first processing sub-circuit, a second processing sub-circuit, and an output sub-circuit. The output sub-circuit includes a first output transistor. The input sub-circuit includes a first input transistor and a second input transistor coupled in series between an input terminal and a first node. The first node is coupled to a gate of the first output transistor. The first processing sub-circuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

A scan circuit is provided. The scan circuit includes a plurality of scan units cascaded. A respective scan unit of the plurality of scan units includes a first subcircuit connected to a first node; a second subcircuit connected to the first node and a second node; a third subcircuit connected to the second node and a third node; a fourth subcircuit connected to a fourth node and a sixth node; and a fifth subcircuit configured to output an output signal through an output terminal, and is connected to the fourth node. The first subcircuit includes an input transistor, a thirteenth transistor, and a fourteenth transistor. A gate electrode of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. A first electrode of the thirteenth transistor is configured to receive an input signal from an input terminal.

A scanning circuit is provided, comprising a first control signal driving circuit, a second control signal driving circuit and a third control signal driving circuit; wherein in a first region, the first control signal driving circuit comprises L levels, L being an integer greater than or equal to 1; in a second region, the second control signal driving circuit comprises M1 levels, and the third control signal driving circuit comprises M2 levels, M1 and M2 being integers greater than or equal to 1; in a third region, the first control signal driving circuit comprises N1 levels, the second control signal driving circuit comprises N2 levels, and the third control signal driving circuit comprises N3 levels, N1, N2 and N3 being integers greater than or equal to 2; and the first region, the second region and the third region respectively surround a first part, a second part and a third part of a periphery of a display region, the first part, the second part and the third part at least partially not overlapping.

A display apparatus includes a display panel(DP), and a scan circuit(SC) configured to provide control signals to the display panel(DP). The plurality of scan units(SU) are grouped into N number of groups, N being a positive integer greater than 2. A respective group of scan units(SU) includes one or more scan units(SU). The scan circuit(SC) further includes N number of control units(CU) connected to the N number of groups of scan units(SU), and N number of selection units(SLU) connected to the N number of control units(CU), respectively. A respective control unit(CU) of the N number of control units(CU) is configured to provide a start signal to the respective group of scan units(SU) of the N number of groups of scan units(SU). A respective selection unit(SLU) of the N number of selection units(SLU) is configured to transmit one or more selection signals to the respective control unit(CU).

A scan circuit is provided. The scan circuit includes a plurality of cascaded scan cells. Each scan cell of the plurality of scan cells includes an input sub-circuit configured to control a voltage level at a pull-up node, and at least three output sub-circuits including a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit, the second output sub-circuit, and the third output sub-circuit are coupled to the pull-up node. The first output sub-circuit, the second output sub-circuit, and the third output sub-circuit are configured to receive clock signals from a first clock signal line, a second clock signal line, and a third clock signal line, respectively. The first output sub-circuit, the second output sub-circuit, and the third output sub-circuit are coupled to a first output terminal, a second output terminal, and a third output terminal, respectively.

The present disclosure discloses a display panel. The display panel includes a scan circuit, a first signal line, and an electrostatic protection unit. The scan circuit includes a plurality of shift registers, where the plurality of shift registers are arranged along a first direction and cascaded. The first signal line is connected to the scan circuit and provides a signal to the scan circuit. The scan circuit and the first signal line are both located in a display region. The electrostatic protection unit is located in the display region and electrically connected to the first signal line.

A display device includes a display panel having an active area and a non-active area, and including a circuit area in which a scan circuit supplying a scan signal to a sub-pixel is positioned and a pixel area having the sub-pixel within the active area, the pixel area and the circuit area being alternately disposed, an inverter circuit located in the non-active area and configured to receive a clock signal supplied to the scan circuit, invert the clock signal, and output an inverted clock signal, a clock line to which the clock signal is applied and which extends along the circuit area and is connected to the scan circuit, and an inverted clock line to which the inverted clock signal is applied and which extends from the inverter circuit along the circuit area, wherein the inverted clock line is adjacent to the clock line and extends in the same direction.

A display panel is provided. The display panel includes a plurality of scan circuits and a plurality of pixel driving circuits. The plurality of scan circuits are at least partially in a display area. A respective scan circuit of the plurality of scan circuits are between adjacent pixel driving circuits of the plurality of pixel driving circuits. The respective scan circuit comprises a plurality of scan units cascaded. Multiple scan units in at least a portion of the respective scan circuit are arranged in a periodic serpentine pattern according to the arrangement position and the cascading relationship of the scan units.

A multi-channel scanning circuit for a capacitive touchscreen includes a switch array connected to each channel. The switch array is also connected to multiple capacitance detection modules. The signal input terminal of each capacitance detection module is connected to an analog-to-digital converter (ADC). The switch array includes multiple switches and a switch control module connected between the switches and the input terminals of the capacitance detection modules. The control logic of the switch control module is to control different capacitance detection modules to connect to different channels in different detection cycles, ensuring that each channel is detected the same number of times by each capacitance detection module. The ADC is also connected to a data processing module. This invention also discloses a multi-channel scanning method for a capacitive touchscreen. The multi-channel scanning circuit for a capacitive touchscreen of this invention, by superimposing the scan values ​​of multiple capacitance detection modules as the scanning result, theoretically eliminates system noise caused by differences between different capacitance detection modules, thus improving capacitance detection accuracy.

A scan circuit is provided. The scan circuit includes a plurality of scan units cascaded. Each scan unit in the plurality of scan units includes a first sub-circuit connected to a first node, a second sub-circuit connected to the first node and a second node, a third sub-circuit connected to the second node and a third node, a fourth sub-circuit connected to a fourth node and a sixth node, and a fifth sub-circuit configured to output an output signal through an output terminal and connected to the fourth node. The first sub-circuit includes an input transistor, a thirteenth transistor and a fourteenth transistor. A gate of the thirteenth transistor is configured to receive a third clock signal from a third clock terminal. A first electrode of the thirteenth transistor is configured to receive an input signal from the input terminal.

The application discloses a timing scanning circuit for scanning diodes, comprising cathode scanning logic circuits and at least two anode scanning logic circuits; each anode scanning logic circuit is used for configuring a level signal at an anode of a diode and an enable signal for controlling generation of the level signal; the cathode scanning logic circuit is used for configuring a level signal at a cathode of all diodes configured by the anode scanning logic circuits and an enable signal for controlling generation of the level signal, so as to drive part or all of the diodes required to be scanned to light up; wherein the cathodes of all the diodes configured by the anode scanning logic circuits are connected together.

A shift register unit and a method for driving same, a row scanning circuit, and a display device. In the shift register unit, a first control circuit (01), under the control of a first clock signal, can control a potential of a first node (n1); a second control circuit (02), under the control of the potential of the first node (n1), a second clock signal, and a first power supply signal, can control a potential of a second node (n2); an adjustment circuit (03), under the control of the potential of the first node (n1), a third clock signal, a control signal, and a target signal, can adjust the potential of the first node (n1), so that the potential of the first node (n1) is stably maintained; and an output circuit (04), under the control of the potentials of the two nodes, can output a fourth clock signal or a second power supply signal via an output terminal (Gout). Thus, by flexibly configuring the clock signals, the shift register unit can flexibly output to a pixel circuit a scanning signal having a high or low potential, thereby meeting the driving requirements of any type of transistor in the pixel circuit.