Multi-core memory system simulator on basis of network-on-chip interconnection

A storage system and network-on-chip technology, applied in the field of multi-core storage system emulators, can solve problems such as interconnection of storage systems, and achieve the effects of speeding up development, reducing inter-core communication delay, improving communication efficiency and data transmission bandwidth

Active Publication Date: 2014-07-09
SUZHOU INST FOR ADVANCED STUDY USTC
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a multi-core storage system emulator based on on-chip network interconnection, which solves the problem of multi-core storage system interconnection

Method used

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  • Multi-core memory system simulator on basis of network-on-chip interconnection

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Embodiment

[0027] This embodiment adopts a new interconnection mode: a network-on-chip interconnection mode. The cache under multi-core adopts a hierarchical structure, using a two-level cache structure. The first-level cache is private to each core, and the second-level cache is shared by each core; since the first-level cache is private to multiple cores, each core caches the same cache block The data in performs different operations, so it is easy to cause data inconsistency.

[0028] 1. Cache module

[0029] The cache module is implemented according to its definition, using group associative mapping strategy, write-back method, and randomly selecting a cache line when replacing. First, a pointer is used to point to the Cache Block. There are many pointers in these cache blocks. These pointers point to the unit that actually stores information. This unit is called a cache line (cache line). Both private caches and shared caches use cache lines, but only the first-level cache needs t...

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Abstract

The invention discloses a multi-core memory system simulator on the basis of network-on-chip interconnection. The multi-core memory system simulator is characterized in that a core of SystemC is used as a driving core of the integral simulator, the multi-core memory system simulator comprises cache modules, a plurality of route modules and QEMU modules, the cache modules are used for simulating primary high-speed caches of cores of various processors, the route modules are used for simulating secondary high-speed caches of the cores of the various processors, and the QEMU modules are used for realizing functional simulation effects; the various route modules are interconnected with networks-on-chip which are formed by the secondary high-speed caches shared by the cores of the simulation processors, and each route module is provided with a group of signal lines connected with the corresponding cache modules; pkt (packet) messages which are transmitted by one cache module or one route module are distributed to another cache module or another route module. The multi-core memory system simulator has the advantages that system software of target systems can be developed by the aid of the simulator, the software and hardware can be simultaneously developed, and accordingly the system development speed can be increased.

Description

technical field [0001] The invention belongs to the field of storage system simulation, and in particular relates to a multi-core storage system simulator based on on-chip network interconnection. Background technique [0002] The early single-core computer system achieved the purpose of improving computer performance by increasing the chip frequency, but it was followed by excessive heat generation and corresponding performance improvement, so multi-core was produced. In order to study the multi-core processor and its on-chip network, the simulation technology of the system structure can be used for simulation, and the running program can be tested and verified. The current mainstream system simulators such as Simplescalar and M5 are mainly analog processors, and each simulator has its own focus. For example, the former mainly simulates the execution process of the processor, and the latter mainly simulates the network host. Few emulators focus on the storage system. Most...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455
Inventor 吴俊敏崔贤芬赵小雨
Owner SUZHOU INST FOR ADVANCED STUDY USTC
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