Inverter and memory device

Abstract

The invention discloses an inverter and a memory device. The inverter includes negative capacitance transistors connected in series and configured to receive a first input level representing a logic value 1, a second input level representing a logic value 1 / 2, and a third input level representing a logic value 0, respectively, a first output level representing a logic value 0, a second output level representing a logic value 1 / 2, and a third output level representing a logic value 1 are output.

Description

technical field [0001] The present application relates to the technical field of semiconductors, and in particular, relates to a three-logic value inverter and a three-logic value storage device. Background technique [0002] CMOS technology has evolved over the years by scaling device dimensions. However, as device density increases, the parasitic capacitance and resistance of the interconnect leads to increased power consumption, and the overall length and complexity of the interconnect increases with each new technology node. These have become bottlenecks that limit the further development of CMOS technology. Contents of the invention [0003] In view of this, it is an object of the present application, at least in part, to provide a triple logic value inverter and a triple logic value storage device that can achieve the same function with fewer devices and interconnections. [0004] According to a first aspect of the present application, there is provided an inverter...

AI Technical Summary

Problems solved by technology

However, as the device density increases, the parasitic capacitance and resistance of the interconnect lines lead to an increase in power consumption, and the overall length and complexity of the interconnect lines increase with each new technology node

These have become bottlenecks that limit the further development of CMOS technology

Images