Substrate for micro electro mechanical system chip, micro electro mechanical system chip and preparation method thereof

Abstract

The invention relates to a substrate for a micro electro mechanical system chip, the micro electro mechanical system chip and a preparation method thereof, and belongs to the field of micromechanics. The substrate for the micro electro mechanical system chip comprises a substrate body and at least one cavity, wherein the substrate body has the upper surface and the lower surface; the at least one cavity is formed in the substrate body; each cavity comprises an upper sub cavity part and a lower sub cavity part in vertical arrangement; the upper sub cavity part and the lower sub cavity part are communicated; the upper sub cavity is formed by downwards extending from the upper surface of the substrate body; the shape and / or the dimension defined by the upper sub cavity part are / is different from the shape and / or the dimension defined by the lower sub cavity part; the positive projection area of the upper sub cavity part is greater than the positive projection area of the lower sub cavity part on the lower surface of the substrate body.

Description

technical field [0001] The invention relates to a substrate for a micro-electromechanical system chip, a micro-electromechanical system chip and a preparation method for the substrate, belonging to the field of micromechanics. Background technique [0002] Micro-Electro-Mechanical Systems (MEMS, Micro-Electro-Mechanical System), also known as micro-electro-mechanical systems, micro-systems, micro-machines, etc., are developed on the basis of microelectronics technology (semiconductor manufacturing technology), integrating lithography, corrosion , thin film, LIGA, silicon micromachining, non-silicon micromachining and precision machining technologies to produce high-tech electromechanical devices. [0003] With the rapid development of the semiconductor industry, through-silicon via etching technology is becoming more and more important, especially in the fields of 3D packaging and MEMS, bulk silicon etching is an essential key step. At present, in the field of through-silic...

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Problems solved by technology

However, this process also has certain limitations. Generally, the etching angle is relatively vertical (by this etching method, a cavity 1 is formed at one time, and the cavity wall of the cavity 1 is a vertical surface 11, such as Figure 1a ), or form an inverted trapezoidal shape with the bottom slightly larger than the top (by this etching method, an inverted trapezoidal cavity 2 is formed at one time, and the cavity wall 21 of the cavity 2 is a slope, such as 1b), or the top is slightly larger than the bottom trapezoidal shape (by this etching method, a positive trapezoidal cavity 3 is formed at one time, and the cavity wall 31 of the cavity 3 is a slope, such as 1c)

In addition, the use efficiency of this structure is low, and the volume of the formed chip is relatively large.

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