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Emulator of Multi-core Memory System Based on On-Chip Network Interconnection

A storage system and network-on-chip technology, which is applied in the field of multi-core storage system emulators, can solve storage system interconnection problems, achieve the effects of accelerating development speed, improving communication efficiency and data transmission bandwidth, and facilitating expansion

Active Publication Date: 2017-12-01
SUZHOU INST FOR ADVANCED STUDY USTC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a multi-core storage system emulator based on on-chip network interconnection, which solves the problem of multi-core storage system interconnection

Method used

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  • Emulator of Multi-core Memory System Based on On-Chip Network Interconnection

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Embodiment

[0027] This embodiment adopts a new interconnection mode: a network-on-chip interconnection mode. The cache under multi-core adopts a hierarchical structure, using a two-level cache structure. The first-level cache is private to each core, and the second-level cache is shared by each core; since the first-level cache is private to multiple cores, each core caches the same cache block The data in performs different operations, so it is easy to cause data inconsistency.

[0028] 1. Cache module

[0029] The cache module is implemented according to its definition, using group associative mapping strategy, write-back method, and randomly selecting a cache line when replacing. First, a pointer is used to point to the Cache Block. There are many pointers in these cache blocks. These pointers point to the unit that actually stores information. This unit is called a cache line (cache line). Both private caches and shared caches use cache lines, but only the first-level cache needs t...

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Abstract

The invention discloses a multi-core storage system emulator based on on-chip network interconnection, which is characterized in that the emulator uses the core of SystemC as the driving core of the entire emulator, and includes a first-level cache for simulating each processor core The caching module, the routing module for simulating the L2 cache of each processor core and the QEMU module for providing functional simulation; several routing modules are connected to the on-chip network formed by the L2 cache shared by the simulation processor cores, Each routing module is provided with a set of signal lines connected to the cache module; the routing module distributes the pkt message delivered by the cache module or the routing module to another cache module or another routing module. The emulator can be used to develop the system software of the target system, so that the software and hardware can be developed simultaneously, and the system development speed can be accelerated.

Description

technical field [0001] The invention belongs to the field of storage system simulation, and in particular relates to a multi-core storage system simulator based on on-chip network interconnection. Background technique [0002] The early single-core computer system achieved the purpose of improving computer performance by increasing the chip frequency, but it was followed by excessive heat generation and corresponding performance improvement, so multi-core was produced. In order to study the multi-core processor and its on-chip network, the simulation technology of the system structure can be used for simulation, and the running program can be tested and verified. The current mainstream system simulators such as Simplescalar and M5 are mainly analog processors, and each simulator has its own focus. For example, the former mainly simulates the execution process of the processor, and the latter mainly simulates the network host. Few emulators focus on the storage system. Most...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/455
Inventor 吴俊敏崔贤芬赵小雨
Owner SUZHOU INST FOR ADVANCED STUDY USTC
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