3 results about "Software simulator" patented technology

The invention discloses a method and system for verifying an RISC-V processor and a computer readable storage medium. The method comprises the following steps: analyzing an RISC-V official manual and a micro-architecture user manual, and generating a static instruction-resource mapping table; and generating a first test instruction sequence for each instruction in the static instruction-resource mapping table, executing the first test instruction sequence by using an RISC-V processor simulation model constructed by a software simulator, and dynamically calibrating the static instruction-resource mapping table in the execution process. And traversing the instruction and resource mapping relationship in the calibrated static instruction-resource mapping table, analyzing RISC-V processor verification logic, and if a conflict is found, outputting a conflict report so as to complete defect repair before RTL code writing. According to the application, hardware behaviors can be accurately associated, the problem of disjunction of semantics and micro-architecture is solved, and conflict prediction in an architecture design stage and end-to-end automatic verification from instruction semantics to micro-architecture behaviors are realized.

A method is provided for identifying a data transfer mismatch between a sender and a receiver from among units of a software simulator of a hardware processor. The simulator runs the plurality of the units which communicate with each other via First-In First-Outs (FIFOs). The method counts amounts of data the sender writes to the FIFOs and the receiver reads from the FIFOs for a given data transfer. The method avoids blocking during FIFO reading and writing operations by (i) reading dummy data by the receiver, even if the FIFOs are empty, when the receiver tries reading from the FIFOs, and (ii) discarding written data if the FIFOs are full, when the sender tries writing to the FIFOs. The method identifies mismatches in the amount of data the sender writes to the FIFOs versus the amount of data the receiver reads from the FIFOs for the given data transfer.

The invention relates to a deep learning acceleration core, in particular to a front-end simulation system and method for the deep learning acceleration core, and a decoding module, which decodes an external test set according to different requirements of software and hardware platforms; the hardware field recovery module is used for determining a hardware simulation starting point according to parameters input by a user, and recovering a hardware simulation field to an initialized state when full-process simulation needs to be carried out; when simulation needs to be started from the synchronization point of the sync instruction, a hardware simulation site is recovered to a position close to the sync instruction; the hardware simulation result output module is used for outputting the type of the current instruction and the corresponding program counting PC to a screen in real time when hardware simulation is carried out, and outputting a hardware simulation result; the software simulator and the result processing module are used for carrying out parameter configuration on the software simulator and outputting a software simulation result; according to the technical scheme provided by the invention, the defects of low efficiency and difficulty in quickly positioning error instructions in the prior art can be effectively overcome.