Method and system for managing event queue of software simulator of microprocessor

Abstract

The invention discloses a method and system for managing an event queue of a software simulator of a microprocessor. The method and the system are used for overcoming the defect in the prior art that the efficiency of the event queue of the software simulator of the microprocessor is low. The method comprises the steps: the event queue is stored in a circular array; the circular array contains a plurality of table entries, and each table entry corresponds to one clock cycle of the software simulator; all the table entries in the circular array are enabled to be in one-to-one correspondence to preset linear chain tables, and a head pointer and a tail pointer of each table entry respectively point to a head element and a tail element of a corresponding linear chain table; each linear chain table stores events, which should be triggered in the clock cycle represented by corresponding table entry; a global cycle pointer is enabled to point to the table entry corresponding to the current clock cycle; after the simulation of one clock cycle ends, the global cycle pointer goes forwards by one table entry. The method and the system disclosed by the invention have very high efficiency in the aspects of event insertion, event query and event removal.

Description

technical field [0001] The invention relates to the simulation technology of a microprocessor, in particular to a management method and system for an event queue of a software simulator of a microprocessor. Background technique [0002] When designing a microprocessor, it is common to first use a software simulator to evaluate various alternatives. Through the software modeling of each component, the function and timing of the microprocessor can be accurately simulated, and the defects and errors in the design can be found quickly. [0003] During simulation, those components that require accurate simulation timing will generate a large number of operations with a certain trigger delay. For example, the memory access component frequently issues data cache access operations, and after the operation is issued, it takes 2 cycles to reach the data cache controller. If the data to be accessed is in the data cache, the data will be returned to the memory access unit after 12 clo...

AI Technical Summary

Problems solved by technology

[0021] The technical problem to be solved by this invention is to overcome the inefficient deficiency of the event queue of the software simulator of the microprocessor in the prior art

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