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1693results about How to "Avoid performance" patented technology

Cycle segmented prefix circuits

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU. Similarly, to read an argument register, an instruction must somehow communicate with the most recent preceding instruction that wrote that register. A cspp circuit can implement such functions by computing for each instruction within a wrap-around instruction sequence the accumulative result of applying some associative operator to all the preceding instructions. A cspp circuit has a critical path gate delay logarithmic in the length of the instruction sequence. Depending on its associative operation and its layout, a cspp circuit can have a critical path wire delay sublinear in the length of the instruction sequence.
Owner:YALE UNIV

System and method of adaptive frequency hopping with look ahead interference prediction

A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g. corrupted header bits) exceeds a predefined threshold, that frequency channel is declared temporarily unusable for that time slot and is replaced with another in accordance with a frequency replacement policy. Periodic interference at a particular frequency, originating from a coexisting system of similar operating parameters, may also be detected at instances that are distant from the timeslots for which that particular frequency is to be used, such that frequency replacement in the hopping sequence can be scheduled ahead of time and collisions would be avoided altogether.
Owner:TEXAS INSTR INC
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