Simulation signal viewing method and system for digital product

Abstract

The invention discloses a simulation signal checking method and a simulation system for a digital product, and the method comprises the steps: reading and recording the state data of all external ports of the digital product in real time when FPGA simulation is carried out on the digital product, and reading and recording all internal state data of the digital product at set intervals; after simulation, when the data of a certain clock period of the digital product needs to be traced back and checked, in the recorded simulation data, reading the internal state data of the digital product and the external port state data of the time point stored at the last time point before the clock period at the moment; and loading the digital product into a software simulator, setting the external portstate data and the internal state data recorded at the time point as the initial state of the digital product, starting the software simulator, and running the software simulator to a clock period required to be checked. By adopting the technical scheme of the invention, all simulation data of any clock period can be quickly backtracked and checked.

Description

technical field

[0001] The invention relates to the field of simulation of digital logic products, in particular to a method and system for viewing simulation signals of digital products. Background technique

[0002] In the design process of digital logic products, it is necessary to use simulation verification to test and verify the correctness of the design. Generally speaking, this link is completed by using a software simulator (Simulator).

[0003] The working principle of the software simulator is: run the design under test (RTL code or gate-level netlist) and test vector (HVL code or non-synthesizable SystemVerilog program) in the simulator, and interact with the interface signals of the design under test and the test vector, Complete the verification process defined in the test vector. Developers can check the value of any test vector, view the value of any port or internal signal of the design under test, or the waveform composed of multiple clock cycles to confir...

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