9 results about "SystemVerilog" patented technology

The invention belongs to the field of chip verification, and relates to a distributed networking verification method and system.The method is based on an existing stand-alone UVM verification environment, a verification assembly is transformed through a SystemVerilog DPI mechanism, a network communication interface is added, and the split verification environment is deployed on a plurality of interconnected simulation hosts respectively; a cross-simulation host interaction channel is established by using a layered communication architecture, and real-time transmission and receiving of interface data are realized; the bridging assembly based on the DPI enables service logic of a single-machine UVM verification environment not to be modified and can adapt to distributed simulation. Parallel simulation of multiple simulation hosts is supported, the resource consumption of a single machine is reduced, a distributed verification environment can be quickly established, a chip post-silicon cluster test can be advanced to an EDA simulation stage, the simulation period is greatly shortened, cross-chip deep logic defects are found in time, and the tape-out risk is reduced.

The application discloses a kind of incremental semantic analysis integrated development environment systems for SystemVerilog hardware design language, comprising: workspace discovery component, for automatically identifying project list and constructing project boundary;Virtual file system component, for maintaining source path and file identification mapping and tracking file status;Incremental semantic database component, for performing local failure and incremental recalculation after source code changes;Semantic capability component, for providing completion, jump, reference, renaming, semantic highlighting, formatting and other capabilities;Protocol scheduling component, for unified scheduling and returning results to requests, notifications, background tasks.The application can perform real-time semantic processing on Verilog / SystemVerilog code in a continuous editing scenario, reduce the delay caused by full recalculation, and improve hardware design and development efficiency.

The invention provides a hardware security module verification method and device based on a UVM and electronic equipment. After a verification instruction is received, an SV test case is started in a UVM environment, a target initialization function is called to initialize a target object, a C trigger function, a C initialization function and a DPI setting function are called, and a C test case is executed to obtain a verification result; in the process of executing the C test case, calling an algorithm function, if the to-be-verified hardware security module needs to be subjected to read-write processing, triggering a target interface read function and / or a target interface write function in the UVM environment through a target interface read packaging function and / or a target interface write packaging function in the C environment, and if the to-be-verified hardware security module needs to be subjected to read-write processing, executing the to-be-verified hardware security module. And executing an operation corresponding to the read-write processing on the to-be-verified hardware security module. In the mode, the data type mapping problem between the systemverilog language and the c language does not need to be considered in the UVM environment, so that the verification efficiency of the hardware security module can be improved.

The invention discloses a UVM and C implementation method for a virtual MCU processor, and the method comprises the following steps: S1, compiling system-level excitation verification compiled by a C language into a shared object through a GCC compiler, and transmitting an address and data contained in the shared object to a SystemVerilog / UVM environment in the form of a keyword import through a DPI method, so as to achieve the purpose that the SystemVerilog language calls the C language; s2, a component AHB UVC is adopted to realize bus reading and writing with a transaction class as a data unit; and writing a task by adopting a SystemVerilog language to realize interrupt type definition, interrupt request, interrupt response, interrupt service, field recovery and time waiting. According to the method, debugging in the verification process can be facilitated, and the efficiency of system-level verification work is remarkably improved.

The invention discloses a CPU instruction set comparison verification method based on an open-source Spike simulator, and the method comprises the steps: taking the Spike simulator as a golden reference model, and constructing a collaborative verification platform; monitoring an instruction submission event in real time, driving Spike to execute a peer-to-peer instruction and comparing the architecture states of the two parties in real time; external interruption and abnormal events are synchronously monitored and synchronized to the Spike simulator, and periodic-level synchronous verification of asynchronous events is achieved; monitoring an access transaction of a peripheral register, extracting an access feature, synchronizing the access feature to a virtual peripheral model in the Spike in real time, and updating a model state to maintain architecture consistency; the state snapshot is exported at the preset breakpoint based on the Spike simulator, the snapshot is loaded in the SystemVerilog environment for state reconstruction and RTL simulation, and defect diagnosis information is output by analyzing a comparison result, so that software and hardware problems are efficiently positioned, and the development efficiency of a CPU chip is improved.

This invention relates to a UVM-based register verification method, platform, and storage medium, belonging to the field of signal processing technology. The method includes the following steps: 1. Creating a register table in a unified format; 2. Creating a program instance and defining various events, starting the program's event loop, and responding to user operations; 3. Reading and checking the format of the register table and calling execution events; 4. When a register check event is triggered, replacing the declared insertion point with the corresponding register in the register table to generate SystemVerilog; 5. When a register model generation event is triggered, extracting register attributes from the register table to generate SystemVerilog; 6. Clearing the user interface through a function; 7. Importing the generated test cases into the corresponding verification environment for compilation and execution. This invention achieves one-click automated generation of various test cases for register checks, without the need for traditional manual intervention.

The application belongs to the chip verification test field and relates to a register and memory operation code unified generation method, which comprises design input specification and output specification, a structured flow table is defined according to the input specification and the output specification, the structured flow table is taken as input, legality checking is carried out, and is abstracted as an atomized operation sequence, an intermediate representation layer is constructed, merging and elimination are implemented, an optimized operation sequence is obtained, and the operation sequence is mapped into a C language and a SystemVerilog language which can be compiled and simulated. The application breaks through the limitations of the prior art in system-level complex scene modeling, cross-language consistent code generation, COSIM simulation environment adaptation and multi-protocol flexible expansion and the like, and provides a systematic, efficient and brand-new solution for the automation of chip verification and software test development processes.

This application discloses a code conversion method, apparatus, electronic device, and computer-readable storage medium, relating to the field of digital integrated circuit design automation technology. The method includes: parsing the SystemVerilog code to be converted to obtain an initial abstract syntax tree; parsing the type mapping relationships of the initial abstract syntax tree and establishing a global type mapping table based on the parsing results; performing semantic equivalence transformations on the syntax nodes in the initial abstract syntax tree based on the global type mapping table to obtain an intermediate abstract syntax tree; optimizing the intermediate abstract syntax tree to obtain a target abstract syntax tree; and generating Verilog code corresponding to the SystemVerilog code based on the target abstract syntax tree. This application can generate standardized, high-quality Verilog code while ensuring functional consistency, and can improve the accuracy, reliability, and overall efficiency of code conversion.

This invention relates to a method for controlling random constraints based on simulation command-line parameters or files. The method includes: declaring at least one random constraint controlled by preset parameter variables in a verification environment implemented in SystemVerilog; independently compiling the verification environment to generate compilation results; starting the simulation based on the compilation results and passing preset-formatted random constraint control information to the simulation tool via the simulation command line, the control information specifying the target value of the preset parameter variables; automatically parsing the random constraint control information passed from the simulation command line during simulation execution; and determining the constraint activation mode based on the current value of the preset parameter variables when the verification environment performs randomization. This invention can effectively reduce the time required for modifying random constraints and recompiling during verification convergence, with the time-saving effect being even more significant in large-scale verification projects.