4 results about "SystemVerilog" patented technology

The application discloses a kind of incremental semantic analysis integrated development environment systems for SystemVerilog hardware design language, comprising: workspace discovery component, for automatically identifying project list and constructing project boundary;Virtual file system component, for maintaining source path and file identification mapping and tracking file status;Incremental semantic database component, for performing local failure and incremental recalculation after source code changes;Semantic capability component, for providing completion, jump, reference, renaming, semantic highlighting, formatting and other capabilities;Protocol scheduling component, for unified scheduling and returning results to requests, notifications, background tasks.The application can perform real-time semantic processing on Verilog / SystemVerilog code in a continuous editing scenario, reduce the delay caused by full recalculation, and improve hardware design and development efficiency.

This invention relates to a UVM-based register verification method, platform, and storage medium, belonging to the field of signal processing technology. The method includes the following steps: 1. Creating a register table in a unified format; 2. Creating a program instance and defining various events, starting the program's event loop, and responding to user operations; 3. Reading and checking the format of the register table and calling execution events; 4. When a register check event is triggered, replacing the declared insertion point with the corresponding register in the register table to generate SystemVerilog; 5. When a register model generation event is triggered, extracting register attributes from the register table to generate SystemVerilog; 6. Clearing the user interface through a function; 7. Importing the generated test cases into the corresponding verification environment for compilation and execution. This invention achieves one-click automated generation of various test cases for register checks, without the need for traditional manual intervention.

This application discloses a code conversion method, apparatus, electronic device, and computer-readable storage medium, relating to the field of digital integrated circuit design automation technology. The method includes: parsing the SystemVerilog code to be converted to obtain an initial abstract syntax tree; parsing the type mapping relationships of the initial abstract syntax tree and establishing a global type mapping table based on the parsing results; performing semantic equivalence transformations on the syntax nodes in the initial abstract syntax tree based on the global type mapping table to obtain an intermediate abstract syntax tree; optimizing the intermediate abstract syntax tree to obtain a target abstract syntax tree; and generating Verilog code corresponding to the SystemVerilog code based on the target abstract syntax tree. This application can generate standardized, high-quality Verilog code while ensuring functional consistency, and can improve the accuracy, reliability, and overall efficiency of code conversion.

This invention relates to a method for controlling random constraints based on simulation command-line parameters or files. The method includes: declaring at least one random constraint controlled by preset parameter variables in a verification environment implemented in SystemVerilog; independently compiling the verification environment to generate compilation results; starting the simulation based on the compilation results and passing preset-formatted random constraint control information to the simulation tool via the simulation command line, the control information specifying the target value of the preset parameter variables; automatically parsing the random constraint control information passed from the simulation command line during simulation execution; and determining the constraint activation mode based on the current value of the preset parameter variables when the verification environment performs randomization. This invention can effectively reduce the time required for modifying random constraints and recompiling during verification convergence, with the time-saving effect being even more significant in large-scale verification projects.