41 results about "SystemVerilog" patented technology

The invention provides a universal platform of verifying compatibility between an intellectual property (IP) core and an advanced microcontroller bus architecture (AMBA) bus interface, which comprises a functional simulation tool, an AMBA bus infrastructure, a third-party verification IP core, a controller, a driver, a stimulus, a checker, an advanced peripheral bus (APB) bridge, an advanced high-performance bus (AHB) master interface, an AHB slave interface and an APB slave interface, wherein all the modules are connected to form an integrated coordinating verification environment by adopting a verification component and hierarchical packaging and interconnections ways provided by a SystemVerilog language and advanced verification methodology (AVM). The platform can verify the compatibility of different types of IP core interfaces, and the development time and cost of the verification platform and a verification method are reduced. The invention also provides the universal method for verifying the compatibility between the IP core and the AMBA bus interface. In the method, excitation is produced more normatively, scientifically and accurately, unnecessary iteration is reduced and the verification time is shortened.

The invention relates to a communication interface method of a processor reference model under multiple simulation and verification platforms, wherein the communication interface method is used for realizing a blockable communication interface between the processor reference model and the verification platforms. The communication interface method comprises the steps of: under a VCS (Verilog Compiler Simulator) simulation and verification platform, defining a transaction-level communication interface according to an interface requirement of the processor reference model, fulfilling the function of a defined interface function to realize the interaction with the processor reference model, compiling an interface definition file and generating a corresponding SystemC/SystemVerilog adapter by using a VCS tool command, and exporting an interface performance function of a subsequent adapter to SystemVerilog by using a DPI (Direct Programming Interface); and under a Questa/Ncsim simulation platform, constructing a SystemC module, defining a member function, exporting a macro interface function embedded in a simulation tool to verilog, and importing the interface function by using an import sentence in the verilog.

The invention discloses a verification method and platform based on a systemVerilog language. The method comprises the steps of generating excitation, compiling the excitation to generate binary data, adding timing sequence information for the generated binary data, inputting the binary data into a chip to be tested according to the timing sequence information, and verifying the chip to be tested according to the binary data input to the chip to be tested and data output by the chip to be tested, wherein the verification environment is achieved through the systemVerilog language. According to the verification method and platform based on the systemVerilog language, a simulation control platform and a self-verification control platform are separated, reutilization is easy; the verification method and platform based on the systemVerilog language have good compatibility, and therefore the verification platform compiled through SystemVerilog can be conveniently transplanted to various kinds of simulation environments; a hierarchical structure is adopted, modules are relatively independent, the complexity of the verification platform is lowered, and the platform can be conveniently maintained and modified in the verification process; the verification accuracy degree is improved, the verification efficiency is greatly improved, the verification time is saved, and verification tasks are finished more quickly.

The invention discloses a SystemVerilog based random verification platform and method, and relates to the field of chip design. The SystemVerilog based random verification platform comprises a Test module, a Generator module, a Driver module, a DUT (device under test) module, a Golden Reference module, a Scoreboard module, a Coverage module, an Environment module and the like, wherein the Test module instantiates environment to start testing; the Generator module generates all test excitation; the Driver module receives the test excitation and drives the DUT module and the Golden Reference module, the Scoreboard module judges the function correctness of the DUT module, and the Coverage module accounts the coverage of the test. By means of the random verification method, interfaces among chips are controlled and monitored, the universality of verification environment is improved, and the verification efficiency is substantially improved.

The invention discloses an SPI verification platform based on a UVM, and belongs to the field of IP verification in integrated circuit design. According to the method for building the module-level reusable verification environment, the connection mode of all components in the verification environment is explained, the definition format of the transaction-level SPI data is given, test cases can beconveniently built in the built verification environment, and convergence of the coverage rate is accelerated. According to the method, the latest UVM verification methodology and the SystemVerilog language are adopted to build a verification environment; the proposed UVM verification environment is concise and expandable, high in portability and easy to reuse; various test scenes can be flexiblyconstructed, constrained random excitation is added, and coverage rate convergence is accelerated.

The invention provides a function tree structure of a microprocessor function validate testing example and an automatic generating method. A method using the function tree structure describes a testing example, the function tree structure has clear structure layer, relationship between various indication and parameter is clear for processing description using programming language; the function tree structure is mapped to a testing example described by SystemVerilog language using Perl language automatically, only needing inputting corresponding indication according with the function tree structure can generate the testing example automatically, according, time for covering the function tree structure into the testing example is reduced and a validity efficiency is increased, and a product without defect come into a market can be realized in a short time; in addition, the method can increase or decrease indication or parameter according with various product based on existing function tree structure that can be suitable for generating the testing example of various product automatically, according, increase reusability of the testing example.

The invention provides a data type conversion-based hardware simulator validation data extraction system. The system comprises a SystemVerilog unit and a SystemC unit, wherein the SystemVerilog is used for receiving input data sent from an external hardware simulator, checking the input data, packing the data into a data package and then sending the data package to the SystemC unit; and the SystemC unit is used for 6 data types defined in SystemVerilog into 6 data types defined in SystemVerilog according to a one-to-one corresponding manner, sending the data package to a software simulator according to the simulation precision of the software simulator, extracting the running result of a tested unit running on the hardware simulator with relatively high efficiency, and comparing the running result with a structure preset in the software simulator on a workstation so as to realize the determination of the running result of the tested unit. The method has the advantages of being flexible in data package, high in simulation speed and flexible in software simulator interface.

The invention provides a method for testing single-packet regular matching logic. A peripheral component interface express (PCIe) simulation model simulates the characteristic of a PCIe bus and receives a host command which comprises a write command and a read command. Compared with the prior art, the method has the advantages that: 1) the efficiency of a program which is compiled by using a SystemVerilog language is quite high, a complicated function can be realized by using smaller code line number, and validation efficiency is improved; and 2) a constraint-based random simulation validation method using the SystemVerilog language is a high-efficiency function validation method, the validation efficiency of the function can be greatly improved, and the functional defect of a product which is sold in the market is avoided.

The present disclosure relates to a computer-implemented method for converting between a SystemVerilog user-defined net (“UDN”) and an IEEE supply net is provided. The method may include providing a value conversion table (“VCT”) definition associated with an electronic circuit design. The method may also include mapping, using at least one processor during a simulation, between a SystemVerilog UDN field and a IEEE supply net field. The method may further include converting at least one value between the SystemVerilog UDN field and the IEEE supply net field based upon, at least in part, the VCT definition.

An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘C’.

The invention discloses a method and device for automatically generating an assertion. The method is used for generating an assertion verification code for a to-be-verified module, and comprises the steps as follows: determining simulation waveform data, a to-be-verified object and a waveform data extraction condition corresponding to the to-be-verified module according to user input; extracting a part of the simulation waveform data meeting the waveform extraction condition from the simulation waveform data of the to-be-verified object as to-be-matched waveform data; calculating the value of the to-be-verified object according to the to-be-matched waveform data; selecting at least one assertion template matched with the value of the to-be-verified object from a plurality of pre-stored assertion modules; and outputting an SVA (SystemVerilog Assertion) code corresponding to the selected assertion module as the assertion verification code of the to-be-verified module. According to the method, the using difficulty of the assertion code in the project development process is lowered and the project progress is guaranteed.

The invention relates to a test excitation generator of a complex algorithm and a control method of the test excitation generator. The test excitation generator comprises a fixed vector generation module, a random vector generation module, a special vector generation module, a time sequence monitoring module, a verification scheme input interface module, a time sequence signal input interface module and a test excitation output interface module. The fixed vector generation module generates excitation such as register reset read-write attributes, and the random vector generation module generates constrained randomized excitation; the special vector generation module generates special excitation which cannot be generated by adopting a SystemVerilog randomization command; the test excitationgenerator obtains a control signal through the verification scheme input interface module, controls different vector generation modules to generate corresponding test excitation, and outputs the testexcitation through the test excitation output interface module; the test excitation generator acquires a control signal through the time sequence signal input interface module, and controls the loading and verification starting of the output test excitation; the time sequence monitoring module monitors state information of the complex algorithm verification system through the time sequence signalinput interface module. The method is suitable for test excitation generation of a complex algorithm realized by pure hardware or software and hardware collaboration, and the quality and efficiency ofcomplex algorithm verification can be effectively improved.

The invention provides an AHB core random verification method based on systemverilog. The method comprises the following steps: reading data of an excitation generating module at the beginning of each period by use of an excitation driving module, and transmitting the data to a to-be-tested IP module; feeding back the data of a slave in the excitation driving module to a host of the excitation generating module at the end of the period by use of a feedback signal collecting module; restraining an allowable input kind list of a next period according to the data provided by the feedback signal collecting module by use of the excitation generating module, and randomly selecting one kind from the allowable input kind list at the beginning of the next period; collecting input-output information of the to-be-tested IP at each period by use of a monitoring check module, printing the input-output information to log, and then checking whether the input-output information meets an assertion requirement; directly comparing whether the judgment meets the requirement of a predetermined protocol according to the state of the IP at a predetermined moment by use of an assertion module.

The invention provides a verification platform and method applied to a securities futures counter. A to-be-tested unit is connected with a coverage rate module, an assertion module is connected with the to-be-tested unit; a configuration module, an upper software excitation module, an excitation module and a client excitation module are respectively connected with the to-be-tested unit and a reference model, and the reference module is in comparison connection with a scoreboard. and the to-be-tested unit is connected with the scoreboard comparison module through the sampling module. The verification platform constructed by using the verification methodology of the UVM is randomized more fully, verification management is performed in combination with scripts and coverage rate analysis reports, convergence can be achieved in a short time, the test efficiency and reliability are greatly improved, a complete reference model is provided on a verification architecture, the expected output ofthe verification platform is achieved by using a systemverilog language, the expected output is compared with the sampled RTL service output and table entry update, the output of a specific module orthe assertion error of a time sequence is directly positioned by giving a fault, and positioning and modifying are easy to achieve.

The invention relates to a SystemVerilog coverage set generation method and device. The method comprises the following steps: writing related information of collected function test points into an Excel document according to a preset rule based on a preset rule; and generating a coverage set based on the Excel document by using a preset script. By the adoption of the technical scheme, a verification worker only needs to quantify the function points in the Excel file through a more friendly input interface, and then the Perl automatically generates the coverage set based on the file so as to improve efficiency. And the problems of large workload and low efficiency of manual writing of the coverage set are avoided.

The invention discloses a universal variable constraint signal randomizing method. According to the method, a four-value variable in a SystemVerilog language is used for representing a constraint relation between signals, the constraint relation is transmitted into a program block through a program interface, the program block analyzes the constraint, and a random variable value meeting the constraint relation is randomly obtained according to the constraint. When control signals with different constraint relations are randomized, the randomization operation of the signals can be simply and conveniently finished under the condition of not increasing codes. The method is simple and convenient to implement, random signals with different constraints are randomized by using one program block,corresponding constraint program codes do not need to be written for different constraint relationships, a code quantity is reduced, and working efficiency is improved.

The invention discloses a multi-core processor function verification platform and method based on a hybrid reference model, and belongs to the technical field of integrated circuits. A hybrid reference model in the platform is composed of an instruction set simulator and a SystemVerilog model. The instruction set simulator is a function precision-level model and is used for verifying whether each instruction in the multi-core processor is correctly executed or not; the SystemVerilog model is a function and time sequence precision level hybrid model and is used for verifying whether the memory access instruction executed by the multi-core processor and the Cache consistency operation process are correct or not. According to different instruction set architectures, verification personnel can directly adopt existing instruction set simulators such as Spike and ARMulator, and the design time cost of a reference model can be effectively shortened. According to the invention, the instruction set simulator and the SystemVerilog model can run at the same time, so that the simulation speed of the verification platform is effectively improved.