18 results about "SystemVerilog" patented technology

The application relates to an interrupt monitoring module verification system and method based on a UVM verification methodology, an advanced verification platform integrating error injection, collection and checking of an interrupt monitoring module is built through a SystemVerilog language, the verification platform comprises a basic test component and an instantiated peripheral, a Cortex-M microcontroller, a storage unit and the interrupt monitoring module to be verified, a real interrupt service program processing process is simulated through interaction between the peripheral and the Cortex-M microcontroller, the verification process of the interrupt monitoring module is more in line with a real use scene, meanwhile, a high randomness of a test case and error injection and a plurality of scene combinations ensure the accuracy and completeness of the verification of the interrupt monitoring module, the synchronization of the interrupt monitoring module to be tested and a verification environment is realized with low configuration cost, and the verification efficiency of the interrupt monitoring module is greatly improved.

The invention relates to the technical field of integrated circuit verification, in particular to a queue-based clock frequency deviation monitoring device, which comprises an initialization module used for setting module-related initialization data; the clock event capturing module is used for monitoring the edge of a clock signal in real time and obtaining the accurate simulation time of the moment; the queue management and reference model module is used for storing timestamp information into a dynamic queue as required; the comparison and report module is used for obtaining the size of the queue, comparing the size of the queue with the alarm upper limit and the alarm lower limit in real time and outputting a corresponding report according to a comparison result, the dynamic distribution and efficient operation characteristics of the SystemVerilog queue are utilized, clock events are stored and processed in real time, long-time and multi-clock-domain continuous monitoring is supported, and the real-time performance of the system is improved. An efficient, reliable and low-cost solution is provided for clock verification of a modern digital integrated circuit, and verification completeness and automation level are greatly improved.

The invention belongs to the field of chip verification, and relates to a distributed networking verification method and system.The method is based on an existing stand-alone UVM verification environment, a verification assembly is transformed through a SystemVerilog DPI mechanism, a network communication interface is added, and the split verification environment is deployed on a plurality of interconnected simulation hosts respectively; a cross-simulation host interaction channel is established by using a layered communication architecture, and real-time transmission and receiving of interface data are realized; the bridging assembly based on the DPI enables service logic of a single-machine UVM verification environment not to be modified and can adapt to distributed simulation. Parallel simulation of multiple simulation hosts is supported, the resource consumption of a single machine is reduced, a distributed verification environment can be quickly established, a chip post-silicon cluster test can be advanced to an EDA simulation stage, the simulation period is greatly shortened, cross-chip deep logic defects are found in time, and the tape-out risk is reduced.

The application discloses a kind of incremental semantic analysis integrated development environment systems for SystemVerilog hardware design language, comprising: workspace discovery component, for automatically identifying project list and constructing project boundary;Virtual file system component, for maintaining source path and file identification mapping and tracking file status;Incremental semantic database component, for performing local failure and incremental recalculation after source code changes;Semantic capability component, for providing completion, jump, reference, renaming, semantic highlighting, formatting and other capabilities;Protocol scheduling component, for unified scheduling and returning results to requests, notifications, background tasks.The application can perform real-time semantic processing on Verilog / SystemVerilog code in a continuous editing scenario, reduce the delay caused by full recalculation, and improve hardware design and development efficiency.

The invention provides a hardware security module verification method and device based on a UVM and electronic equipment. After a verification instruction is received, an SV test case is started in a UVM environment, a target initialization function is called to initialize a target object, a C trigger function, a C initialization function and a DPI setting function are called, and a C test case is executed to obtain a verification result; in the process of executing the C test case, calling an algorithm function, if the to-be-verified hardware security module needs to be subjected to read-write processing, triggering a target interface read function and / or a target interface write function in the UVM environment through a target interface read packaging function and / or a target interface write packaging function in the C environment, and if the to-be-verified hardware security module needs to be subjected to read-write processing, executing the to-be-verified hardware security module. And executing an operation corresponding to the read-write processing on the to-be-verified hardware security module. In the mode, the data type mapping problem between the systemverilog language and the c language does not need to be considered in the UVM environment, so that the verification efficiency of the hardware security module can be improved.

A method to generate a hardware design for an electronic device wherein a digital hardware design under test (DUT) for the electronic device is received in a test environment, the digital hardware DUT having an input with a connected buffer; receiving assertions relating to the digital hardware DUT and the buffer; inputting watched data into the buffer; using a state machine to verify the assertions; detecting a deadlock or livelock in the digital hardware DUT in dependence on the verification; and in response to detecting a deadlock or livelock in the digital hardware, providing an output indicative of a deadlock or livelock state detected in the digital hardware DUT. The method may be used in simulation verification or formal verification, e.g. dynamic simulation, particularly for system-on-chip (SoC) designs where computing elements are connected by a fabric or a bus. The DUT may be a high-level language description of a component of a SoC. The buffer may be part of the DUT or a test bench and the watched data may be symbolic data. Assertions may be provided in SystemVerilog Assertions (SVA), Property Specification Language (PSL) or Open Verification Language (OVL). The state machines may be finite state machines (FSM).

The invention relates to the technical field of chip design automation, and discloses a SystemVerilog dynamic constraint increment solving method and system based on hierarchical dependency, and the method comprises the steps: analyzing a SystemVerilog constraint semantic structure, and constructing a solving dependency graph between random variables; performing hierarchical distribution according to the solution dependency graph, dividing variables into solution blocks of different hierarchies, and ensuring that independent variables are preferentially solved; self-adaptively generating and maintaining random variables and constraint conditions in the corresponding solving blocks according to the characteristics of scale change of the dynamic data structure; an incremental updating strategy is adopted, only the affected solving blocks are updated, and the historical state reserved by a solver is reused for local solving, so that a dynamic constraint solving framework based on hierarchical solving dependency analysis, incremental constraint management and solving incremental calling is realized; the method aims at providing an efficient constraint solution scheme for a complex dynamic data structure in hardware verification, and the verification efficiency is remarkably improved by analyzing a constraint relation, optimizing a solution process and reusing solver information.

The invention discloses a UVM and C implementation method for a virtual MCU processor, and the method comprises the following steps: S1, compiling system-level excitation verification compiled by a C language into a shared object through a GCC compiler, and transmitting an address and data contained in the shared object to a SystemVerilog / UVM environment in the form of a keyword import through a DPI method, so as to achieve the purpose that the SystemVerilog language calls the C language; s2, a component AHB UVC is adopted to realize bus reading and writing with a transaction class as a data unit; and writing a task by adopting a SystemVerilog language to realize interrupt type definition, interrupt request, interrupt response, interrupt service, field recovery and time waiting. According to the method, debugging in the verification process can be facilitated, and the efficiency of system-level verification work is remarkably improved.

The application relates to the chip technical field, in particular to a register configuration method based on software and hardware, electronic equipment and medium, which comprises the following steps: S1, generating original register configuration instructions based on a software configuration module; S2, determining register addresses corresponding to register names based on a register address mapping table; S3, inputting the register names corresponding to the original register configuration instructions and the corresponding register addresses into a direct programming interface in a configuration interface module to generate target register configuration instructions based on a SystemVerilog language; S4, calling a test sequence module based on the target register configuration instructions to generate a test task sequence; and S5, calling a driving module to input the test task sequence into a chip design to be tested, and performing corresponding register configuration operations in the chip design to be tested based on the test task sequence. The application improves chip development efficiency and reduces chip development cost.

The invention belongs to the field of chip verification testing, and relates to a register and memory operation code unified generation method, which comprises the steps of designing an input specification and an output specification, defining a structured process table according to the input specification and the output specification, taking the structured process table as input, performing analysis and legality check, abstracting the structured process table into an atomization operation sequence, and constructing an intermediate presentation layer, implementing merging and digestion to obtain an optimized operation sequence, and mapping the optimized operation sequence into a compilable and simulatable product of the C language and the SystemVerilog language. According to the method, the limitation of the prior art in the aspects of system-level complex scene modeling, cross-language consistency code generation, COSIM simulation environment adaptation, multi-protocol flexible extension and the like is broken through, and a systematic and efficient brand-new solution is provided for automation of chip verification and software test development processes.

The invention discloses a CPU instruction set comparison verification method based on an open-source Spike simulator, and the method comprises the steps: taking the Spike simulator as a golden reference model, and constructing a collaborative verification platform; monitoring an instruction submission event in real time, driving Spike to execute a peer-to-peer instruction and comparing the architecture states of the two parties in real time; external interruption and abnormal events are synchronously monitored and synchronized to the Spike simulator, and periodic-level synchronous verification of asynchronous events is achieved; monitoring an access transaction of a peripheral register, extracting an access feature, synchronizing the access feature to a virtual peripheral model in the Spike in real time, and updating a model state to maintain architecture consistency; the state snapshot is exported at the preset breakpoint based on the Spike simulator, the snapshot is loaded in the SystemVerilog environment for state reconstruction and RTL simulation, and defect diagnosis information is output by analyzing a comparison result, so that software and hardware problems are efficiently positioned, and the development efficiency of a CPU chip is improved.

The invention relates to the technical field of integrated circuit design verification, and discloses a relaxation constraint-based over-constraint excitation positioning method, system and device, and the method achieves the automatic recognition of the over-constraint in a test platform through a systematic relaxation constraint method, and solves the problems of high concealment and low recognition efficiency of the over-constraint in the prior art. The excessive constraint can be quickly identified, the coverage rate loss and the simulation resource waste caused by the constraint problem are reduced, the chip verification period is shortened, and the project cost is reduced; hidden excessive constraints which are difficult to find by traditional coverage rate analysis can be identified; and the method is suitable for various test platforms based on SystemVerilog, and particularly has outstanding performance in integration-level complex design.

The application discloses an implementation method for a RISC-V physical memory protection mechanism, and comprises the following steps: according to the RISC-V ISA specification, analyzing the physical memory protection mechanism module structure, the input and output of the module, designing the module framework according to the document requirements, and then using the SystemVerilog language to implement the module; according to the ISA specification, performing property analysis on the PMP module, classifying the properties obtained through the analysis, and using a formal language to describe the properties; based on the implemented physical memory protection module, combining the extracted properties, using the assertion-based formal verification tool Symbiyosys to perform formal verification on the properties, and integrating the verification results to ensure the correctness of the RISC-V physical memory protection mechanism.

This invention relates to a UVM-based register verification method, platform, and storage medium, belonging to the field of signal processing technology. The method includes the following steps: 1. Creating a register table in a unified format; 2. Creating a program instance and defining various events, starting the program's event loop, and responding to user operations; 3. Reading and checking the format of the register table and calling execution events; 4. When a register check event is triggered, replacing the declared insertion point with the corresponding register in the register table to generate SystemVerilog; 5. When a register model generation event is triggered, extracting register attributes from the register table to generate SystemVerilog; 6. Clearing the user interface through a function; 7. Importing the generated test cases into the corresponding verification environment for compilation and execution. This invention achieves one-click automated generation of various test cases for register checks, without the need for traditional manual intervention.

The application belongs to the chip verification test field and relates to a register and memory operation code unified generation method, which comprises design input specification and output specification, a structured flow table is defined according to the input specification and the output specification, the structured flow table is taken as input, legality checking is carried out, and is abstracted as an atomized operation sequence, an intermediate representation layer is constructed, merging and elimination are implemented, an optimized operation sequence is obtained, and the operation sequence is mapped into a C language and a SystemVerilog language which can be compiled and simulated. The application breaks through the limitations of the prior art in system-level complex scene modeling, cross-language consistent code generation, COSIM simulation environment adaptation and multi-protocol flexible expansion and the like, and provides a systematic, efficient and brand-new solution for the automation of chip verification and software test development processes.

The invention discloses a system verilog and C language mutual conversion method, which relates to the field of digital chips and comprises the following steps: acquiring an original file, and respectively extracting common keywords, keyword categories and keyword detailed description information of a system verilog programming language and a C language; a SystemVerilog and C language keyword corresponding table is constructed, and the keyword corresponding table is used for establishing a mapping relation between keywords of the two languages and providing a keyword matching basis for code conversion; storing the content of the keyword corresponding table in the form of a dictionary data structure by using a script language, wherein the dictionary uses key value pairs to store keywords of SystemVerilog and c language which are matched with each other; storing paths or names of all original files needing to be converted in a list data structure by using a script language; and traversing each original file in the list to perform language conversion. According to the method, rapid and efficient conversion between the SystemVerilog and the C language is realized by utilizing the script file.

This application discloses a code conversion method, apparatus, electronic device, and computer-readable storage medium, relating to the field of digital integrated circuit design automation technology. The method includes: parsing the SystemVerilog code to be converted to obtain an initial abstract syntax tree; parsing the type mapping relationships of the initial abstract syntax tree and establishing a global type mapping table based on the parsing results; performing semantic equivalence transformations on the syntax nodes in the initial abstract syntax tree based on the global type mapping table to obtain an intermediate abstract syntax tree; optimizing the intermediate abstract syntax tree to obtain a target abstract syntax tree; and generating Verilog code corresponding to the SystemVerilog code based on the target abstract syntax tree. This application can generate standardized, high-quality Verilog code while ensuring functional consistency, and can improve the accuracy, reliability, and overall efficiency of code conversion.

This invention relates to a method for controlling random constraints based on simulation command-line parameters or files. The method includes: declaring at least one random constraint controlled by preset parameter variables in a verification environment implemented in SystemVerilog; independently compiling the verification environment to generate compilation results; starting the simulation based on the compilation results and passing preset-formatted random constraint control information to the simulation tool via the simulation command line, the control information specifying the target value of the preset parameter variables; automatically parsing the random constraint control information passed from the simulation command line during simulation execution; and determining the constraint activation mode based on the current value of the preset parameter variables when the verification environment performs randomization. This invention can effectively reduce the time required for modifying random constraints and recompiling during verification convergence, with the time-saving effect being even more significant in large-scale verification projects.