Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Multi-core processor function verification platform and method based on hybrid reference model

A multi-core processor and reference model technology, which is applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of increased difficulty in reference model design and a large amount of time spent by verification personnel.

Pending Publication Date: 2021-07-06
JIANGNAN UNIV
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that the design difficulty of the reference model suddenly increases due to the complexity of the existing multi-core processor, and verification personnel usually need to spend a lot of time to build the reference model, the present invention provides a multi-core processor based on a hybrid reference model Function verification platform and method

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-core processor function verification platform and method based on hybrid reference model
  • Multi-core processor function verification platform and method based on hybrid reference model
  • Multi-core processor function verification platform and method based on hybrid reference model

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] This embodiment provides a mixed reference model of a multi-core processor function verification platform based on a mixed reference model, see figure 1 The hybrid reference model is composed of an instruction set simulator and a Systemverilog model; the instruction set simulator is a functional precision level model for verifying whether each instruction in the multi-core processor is correctly executed correctly; SystemverIlog model is functional and timing accurate level The mixing model is used to verify that the interview instruction executed by the multi-core processor and whether the Cache consistency operation process is correct. The SystemVerilog model includes control logic, a cache status history table, and an intermittent request queue for a Cache consistency protocol.

[0035] It is to be described, and the verifier can effectively shorten the design time overhead of the reference model directly with an existing instruction simulator, such as Spike, Armulator, ...

Embodiment 2

[0037]This embodiment provides a multi-core processor function authentication method based on a mixed reference model, and the multi-core processor system to be tested is a RISC-V multicore processor system as an example, the multi-core processor function based on a mixed reference model. The verification platform includes a multi-core processor system (DUT), a test excitation generator, a hybrid reference model, and the SYSTEMVERILOG language-based monitoring module and a scoreboard; where the multi-core processor system is RISC. -V multicore processor system.

[0038] Such as figure 2 As shown, the monitoring module monitors the status conversion and timing relationship generated in the Cache consistency operation process generated in the Cache consistency operation process of the DUT and the SYSTEMVERILOG model for each execution of the NUT and the SYSTEMVERILOG model. And control the synergy of the instruction set simulator and the SystemverIlog model.

[0039] The verificatio...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a multi-core processor function verification platform and method based on a hybrid reference model, and belongs to the technical field of integrated circuits. A hybrid reference model in the platform is composed of an instruction set simulator and a SystemVerilog model. The instruction set simulator is a function precision-level model and is used for verifying whether each instruction in the multi-core processor is correctly executed or not; the SystemVerilog model is a function and time sequence precision level hybrid model and is used for verifying whether the memory access instruction executed by the multi-core processor and the Cache consistency operation process are correct or not. According to different instruction set architectures, verification personnel can directly adopt existing instruction set simulators such as Spike and ARMulator, and the design time cost of a reference model can be effectively shortened. According to the invention, the instruction set simulator and the SystemVerilog model can run at the same time, so that the simulation speed of the verification platform is effectively improved.

Description

Technical field [0001] The present invention relates to a multi-core processor function verification platform and method based on a mixed reference model, belonging to the technical field of integrated circuits. Background technique [0002] With the rapid development of integrated circuit technology, more and more kernels are integrated on the same chip, and the multi-core processor has become a mainstream architecture for processor design. However, in order to meet the growing high-performance demand, the size of the processor is increasing, and its function complexity is also increasing, which has brought huge challenges for the verification of multi-core processors. [0003] At present, the mainstream functional verification methods are: form validation, hardware acceleration verification, and simulation-based feature verification. Among them, the simulation-based functional verification method is the most widely used in the verification of multi-core processors. Simulation-b...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F30/3308G06F115/10
CPCG06F30/3308G06F2115/10
Inventor 虞致国李青青顾晓峰
Owner JIANGNAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com