431 results about "Simics" patented technology

The invention provides a cross-platform low-code application development system based on a Flutter framework. Comprising a login registration module, a project management module, an interface design module, a state management module, a route management module, a team management module, a help document module, an AI page design module, a development document generation module, a hardware integration module, a code generation module, a multi-user collaborative development module, a communication module, an online simulator module, an AI generation application module and an interface management module. An asset management module, a developer forum module, an application market module and an application packaging module. The communication module supports various communication protocols and secure transmission modes, and ensures that data exchange applied to cross-platform and cross-system environments is secure and reliable. Through component dragging and graphical configuration, the low-code platform automatically analyzes configuration data to generate an App, a development document and a source code. And meanwhile, multi-person collaborative development is supported, so that the development threshold is reduced and the development speed is increased.

The invention relates to the technical field of artificial intelligence chips, and discloses a model performance estimation method and device and computer equipment, and the method comprises the steps: determining model configuration data and candidate distributed strategies of a target model; converting the original calculation graph corresponding to the single-card deployment state based on the model configuration data and the strategy configuration data of the candidate distributed strategies to obtain a distributed overhead calculation graph corresponding to the multi-card deployment state; and performing performance estimation on the candidate distributed strategy according to the basic overhead and the additional overhead in the distributed overhead calculation graph to obtain strategy performance data of the target model under the candidate distributed strategy, thereby realizing conversion of a single-card model into a multi-card model. And based on the multi-card model, simulation calculation of the multi-card interconnection mode is realized on the premise of limited hardware resources, so that the influence of a communication operator and a topological structure corresponding to the multi-card interconnection mode in the overall operation of the model is reflected, and the upper limit of the model performance can be accurately evaluated in a simulator verification stage before silicon is applied.

A platform for multi-stage simulations in a multi-agent simulator computing system utilizes context sharing across simulation sessions. The platform generates agents based on input traits, executes simulation sessions to produce outputs, and persists outputs and agent configuration data (e.g., metadata associated with simulation sessions). A graphical user interface displays simulation outputs. In response to user interaction with a particular output item (e.g., a user follow-up query or inquiry into simulation traceability), the platform identifies the associated agent using persisted configuration data and performs additional operations, which can include generation and execution of additional queries for follow-up simulations.

The invention relates to the technical field of processor design and test, and discloses an instruction sequence generation method for verifying floating point operation of a processor, which comprises the following steps: constructing a floating point test coverage model, generating a floating point test database, and constructing a basic RISC-V instruction sequence generator; adding a register updating mechanism bound with a memory on the basis of the basic instruction RISC-V sequence generator, and generating initialized data of the memory; and injecting the generated instruction machine code and the memory initialization data into the memory of the processor to be verified for simulation, and comparing the execution track obtained by simulation with the execution track of the instruction set simulator to find potential errors in the processor. According to the method, an efficient coverage model is constructed to generate representative floating point test data, a floating point data path of the processor can be verified more comprehensively, the defects of an existing method in the aspect of floating points in the RISC-V instruction generation process are overcome, and potential design defects in the processor are found.

A computing platform can generate a virtual world and a set of virtual agents having agent traits and interaction rules. For example, by automatically analyzing experimenter queries, the platform can bind the agents to machine learning models that perform tasks responsive to the questions. The platform can generate additional hypotheticals to enable chains of simulations. The platform can execute a first simulation session by causing the set of agents to generate a first output set. Using an additional data source to generate new world characteristics, such as environmental and / or temporal conditions, the platform can generate and apply agent evolution logic for subsequent simulations, such as by performing mutation of agent traits, selection of agents, crossover of agent characteristics, and / or deletion of agents that do not meet a fitness threshold. The platform can persist agent states and outputs to generate user-interactive visualizations, aggregations, and training data sets for training agent models.

The invention discloses a reinforcement learning calculation simulation method and device, electronic equipment and a storage medium, and relates to the technical field of artificial intelligence computing, and the method comprises the steps: inputting the determined current model parameter configuration, current hardware configuration and current working load into a target simulation system to obtain a plurality of parallel grouping combinations, determining a target simulation system according to the current hardware configuration, determining an effective parallel packet combination from the plurality of parallel packet combinations based on a preset Monte Carlo method, inputting the effective parallel packet combination into a simulator of a preset neural network model, and performing delay time calculation according to the effective parallel packet combination through the simulator to obtain a delay time sequence; and the combination corresponding to the shortest delay time is used as a target parallel grouping combination, so that the technical problems of mismatching of simulation scenes, insufficient precision and lack of effective support for heterogeneous clusters are solved, reliable performance prediction and optimal parallel strategy suggestions are provided through high-precision performance modeling and automatic exploration, and the method is suitable for large-scale popularization and application. Therefore, the resource consumption of large-scale GRPO training is reduced.

Methods, systems, and storage media for running unified simulations on clusters. Exemplary implementations may include: receiving simulation parameters for a simulation of a cluster; generating synthesized workload events based the simulation parameters of the cluster; determining a memory latency associated with the cluster; determining a reliability and availability of resources in the cluster for a predetermined duration of time; simulating events for jobs in the cluster based on the reliability and availability of resources in the cluster, each job associated with one or more synthesized workload events; and outputting simulation results based on the synthesized workload, the memory latency, and the events.

The invention provides an intelligent teaching-assistant system base LLM training method for a drilling simulator, and belongs to the technical field of petroleum drilling large language model training, and the method comprises the steps: obtaining the simulation data of the drilling simulator based on an intelligent teaching-assistant system base large language model, and carrying out the field self-adaptive pre-training; performing fine adjustment on the original weight by utilizing low-rank self-adaption, and performing operation steps and fault diagnosis generation; the method comprises the following steps: constructing an enterprise private knowledge base, training a large language model by utilizing retrieval enhancement generation, and obtaining a trained verification header through explicit supervision; a direct preference optimization loss function is defined, a direct preference optimization loss function of retrieval perception is obtained in combination with the verification head, the large language model is optimized, and large language model training is completed; according to the invention, an external professional knowledge base can be fused, an equipment operation mechanism can be understood, an intelligent assistant architecture with teaching guidance and error diagnosis capabilities is provided, and the intelligent level of the drilling simulator is improved.

The present application relates to the technical field of computers, and provides an interruption control method and apparatus, an electronic device, a computer program, and a computer-readable storage medium. The method comprises: acquiring a first execution result of a design under test for a benchmark test program and a second execution result of a software emulator for the benchmark test program; and when an interruption condition is satisfied, interrupting the operation of the design under test, wherein the interruption condition comprises at least one of the following: the first execution result does not match the second execution result; a hardware buffer zone corresponding to the design under test is full; the hardware buffer zone is used for recording operation data of the design under test; a software buffer zone corresponding to the software emulator is empty; and the software buffer zone is used for recording operation data of the software emulator. According to embodiments of the present application, in hardware verification, the execution results of the design under test and the software emulator can be automatically compared and checked, and interruption can be automatically triggered, thereby achieving a better debugging capability.

The invention relates to a software and hardware co-simulation chip verification method, system and device and a storage medium, and relates to the field of software and hardware co-simulation. The method is based on a hyperSemu system comprising an hsComple and an hsRun and an FPGA (Field Programmable Gate Array) comprising a DUT (Device Under Test) and a Transactor. The method comprises the following steps of: writing an RTL (Real Time Language) design code of a chip; compiling the RTL design code by utilizing hsCompile to obtain a DB file; downloading the DB file to an FPGA (Field Programmable Gate Array) through hsRun so as to carry out hardware simulation; according to the DUT and the Transactor, a Hybrid server program and a Hybrid client program are written, and the Hybrid client program comprises a simulator program and a Linux system; and performing software simulation in the Linux system according to the DUT and the simulator program. The technical effect of the invention is that the efficiency and speed of chip simulation verification are improved.

The invention is suitable for the technical field of artificial intelligence, and provides a data processing method and device for a big language model based on federal learning, and the method comprises the steps: decomposing the big language model, and obtaining an adapter and a simulator; performing layer compression processing on the simulator to obtain a compression simulator, and deploying the adapter and the compression simulator to a plurality of clients; obtaining adapter parameters uploaded by each client after training the adapter based on a local data set; performing global aggregation on universal adapter parameters in the adapter parameters, and performing grouping aggregation on personalized adapter parameters in the adapter parameters to obtain aggregated adapter parameters; and outputting the aggregated adapter parameters to the client. According to the scheme, privacy protection can be realized, and individual user preferences are reserved.

In various examples, synthetic dataset regeneration for AI systems and applications is described herein. For instance, systems and methods described herein may use a simulator to generate a synthetic dataset along with data (referred to, in some examples, as “log data”) representing information associated with the generation of the synthetic dataset by the simulator. For instance, the log data may represent at least parameters used to generate synthetic dataset, values for the parameters, assets associated with the parameters, and / or values representing results associated with the synthetic dataset. The systems and methods may then use the log data to recreate, modify, and / or enhance the synthetic dataset. For example, the synthetic dataset may be recreated by providing at least the log data as input to the simulator such that the simulator regenerates the dataset using the same parameters, values, and / or assets.

The invention provides an information synchronization method, system and device for an embedded training simulator and a medium. The information synchronization method comprises the steps that task event information in the embedded training simulator is obtained; performing task classification on each piece of task event information to obtain each piece of task event information with attribute tags; according to the attribute tag of each task event information, performing task priority classification on each task event information by using an improved multi-factor priority scoring algorithm to obtain a task priority queue; according to the task priority queuing queue, generating a to-be-pushed data packet, and performing information synchronization on the to-be-pushed data packet; according to the invention, by introducing a task priority-based scheduling mechanism, the pushing sequence and the synchronization strategy of the task information are dynamically optimized, so that the scheduling rhythms and the transmission paths of the tasks with different priorities are intelligently distributed; and the dynamic adaptive capacity and the efficient task delivery capacity of the embedded training simulation in the training process can be improved.

In one embodiment, a method may receive a request to upgrade software for a switch. The method may use an application-specific integrated circuit (ASIC) simulator to generate a digital twin to store a first image and a first configuration of the switch. The method may use the digital twin to generate a second image and a second configuration by replaying the first configuration on the first image. The method may communicate the second image and the second configuration from the digital twin to an ASIC memory of an ASIC associated with the switch by applying batch direct memory access (DMA).

Coaching simulator systems and methods, and non-transitory computer readable media, include receiving an interaction between a customer and an agent; scoring the interaction using an evaluation form; identifying a recurring improvement area for the agent based on the scored interaction and past scored interactions; creating a prompt for a large language model (LLM) by populating a prompt template; providing a framework to invoke the LLM using the created prompt, a model and a plurality of hyperparameters; starting a first coaching simulation scenario by invoking the LLM to present a first question to the agent; receiving a first answer to the first question from the agent; querying the LLM to analyze the first answer to the first question; and querying the LLM to provide real-time feedback and a score for the agent based on the analyzed first answer to the first question.

A non-transitory computer readable medium is provided comprising instructions that when executed on a processor load a software program into a software debugger for execution on an emulated processor representing a processor portion of a system on chip (SoC), load a hardware design into a hardware simulator representing a programmable gate array portion of the SoC, coordinate execution of software debugger and hardware simulator to simulate operation of the SoC, communicate data between the software debugger and the hardware simulator, and display computed results and current values.

Virtual platform system for use in a cloud-based system, comprising: a virtual platform simulator configured to represent in software a physical remote client device and to have this representation interact with a virtual platform application; a process virtual machine configured to execute program instructions of the virtual platform application and comprising a code morpher component for transforming the program instructions of the virtual platform application into native program instructions for execution on a physical host machine of the cloud-based system; and interception components for capturing transactions from the virtual platform simulator and the process virtual machine. The transactions are related to the execution of the program instructions of the virtual platform application. The virtual platform system is configured to compare the captured transactions with pre-stored transactions, preferably stored in a blockchain, to obtain a comparison result, and to allow the execution of the program instructions depending on the comparison result.

Apparatus and method achieve topology optimization with bidirectional mesh adaptation. A mesh engine generates a mesh for a geometry of a computer aided design model of a design domain. A multi-physics simulator derives of physical field variables on the mesh based on material properties and boundary conditions of the design domain. An adjoint sensitivity is determined based on a given cost function and sensitivity formulation to drive a design variable lower or higher, the design variable defining a density of the design domain. An optimizer determines an optimization yielding a new set of design variables based on the adjoint sensitivity. A bidirectional mesh adaptation is performed on regions of the mesh by coarsening or refining the mesh element size. The multi-physics simulation, optimization and mesh adaptation are iteratively performed until optimized convergence criteria are met.

A platform for adaptive multi-agent simulation in a virtual world instantiates a set of agents with input traits and executes a simulation session, generating an output set. Upon detecting a change event in the virtual world, a trained model recommends an evolution operation, which is applied to the set of agents to generate an evolved set. The evolution operation includes mutation, selection, crossover, deletion of agents, or a combination thereof. The platform persists at least a portion of the initial output set and executes a second simulation operation using the evolved agents, generating a new output set and thereby enabling analysis and comparison of simulation results. The disclosed adaptive simulation approach with persisted context enables realistic and dynamic modeling of complex systems.

The invention relates to a reconfigurable equipment simulation system based on software radio, and the system achieves the high-integration, user-friendly and efficient-management reconfigurable equipment simulation system through the modularization and seamless integration of a radio waveform design function, an equipment simulation user operation interface design, a business logic function design and a project management function. Therefore, even if a user does not have a deep programming capability, the user can quickly construct, test, manage and deploy the equipment simulator with complete functions. The system is rich in waveform component and UI component library, customizable in function and good in flexibility, software radio waveform design and equipment simulation are innovatively and seamlessly integrated, automatic non-inductive or manual upgrading can be achieved, the universality is good, various equipment simulators can be designed, the designed equipment simulators have open function expansion, and the system is suitable for popularization and application. And a complete project management process is provided.

The invention belongs to the technical field of computers, and discloses a simulator starting acceleration method and device, equipment and a storage medium, and the method comprises the following steps: obtaining a pre-read block set; performing priority ranking on the data blocks according to the access frequency labels to obtain a pre-read block sequence; extracting a preset number of high-priority data blocks from the pre-read block sequence to generate a target pre-read block subset; executing a pre-reading operation on the target pre-reading block subset to obtain pre-loaded data; storing the preloaded data in a cache, and generating a preloaded cache; in response to a simulator starting instruction, reading the preloading cache to obtain starting data; initializing the simulator according to the starting data to obtain an initialized simulator environment; and executing a simulator starting process by adopting the initialized simulator environment. According to the invention, the starting speed of the simulator can be improved under the condition that the personalized requirement of a user on simulation precision is met.

The invention discloses a controller simulation system construction method and device, equipment and a medium, relates to the technical field of simulation, is applied to a preset transaction-level component, and comprises the following steps: connecting a simulation model of a controller and equipment based on a nonvolatile memory host controller interface specification, and connecting a preset virtual operating system simulator through an inter-process communication component; converting a first transaction level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message; and converting a second transaction layer data packet message sent by the simulation model into a second transaction level modeling message, and sending the second transaction level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction level modeling message, and realizing connection communication between the preset virtual operating system simulator and the simulation model so as to construct the simulation system. And the construction of the controller simulation model is realized.

The invention discloses a core particle simulation platform design method and device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the steps: determining a first topological structure of a core particle simulation platform; the first topological structure comprises a controller and a plurality of core particle nodes; determining a second topological structure of the controller; the controller is used for realizing operation control on the core particle simulation platform; determining a third topological structure of each core particle node; each core particle node comprises a core particle assembly and an external assembly; configuring a plurality of core particle nodes to be tested in the core particle simulation platform; and controlling the plurality of to-be-tested core particle nodes to be tested by using the controller. Compared with a system structure simulator, the core particle simulation platform and the core particle simulation process have the advantages that hardware-level verification can be carried out, more accurate actual core particle behaviors can be obtained, higher running speed is achieved, and various types of core particles can be supported more easily; compared with a traditional FPGA verification platform building method, the method is simpler and more suitable for a core particle design mode.

The invention provides a simulator networking interface code generation method and device, equipment and a medium, and the method comprises the steps: disassembling a nested structure body in a target interface definition language file, and obtaining the information of the disassembled structure body; generating a first interface control document corresponding to the data distribution service network according to the disassembled structure body information; generating a second interface control document corresponding to the simulator network according to the first interface control document and a simulator network data definition rule; and generating a simulator networking interface code according to the data distribution service data definition rule, the simulator network data definition rule and the second interface control document. According to the method, networking between the data distribution service and the simulator can be achieved, manual interface definition and butt joint do not need to be manually conducted in the whole process, the development speed and development efficiency of networking between the data distribution service and the simulator are improved, and human factor errors caused by manual interface processing are effectively avoided.

A method can include receiving property data for a simulation model; analyzing the property data with respect to geometry of the simulation model to select a matrix preconditioner scheme using a machine model; and executing a computational simulator that implements parallel processing based on application of the matrix preconditioner scheme to a matrix representing the simulation model to generate simulation results based on the property data.

The invention provides a steer-by-wire fault degradation processing method, device and equipment and a medium, and belongs to the technical field of intelligent driving fault processing, and the method comprises the steps: obtaining the fault information of each redundant subsystem in system components in real time, and determining the current component state level of each system component; executing corresponding fault processing measures according to the current component state level; wherein the system assembly comprises a lower steering engine and a road feeling simulator, and the fault information comprises no fault, failure fault and degradation fault. According to the technical scheme provided by the embodiment of the invention, the corresponding processing operation can be executed according to the current component state level of each system component, so that the degradation fault and the failure fault of the redundant drive-by-wire system can be accurately processed.

Systems and methods for using distributed quantum-based computing simulators are disclosed. In one embodiment, a method may include: (1) receiving, at a driver node and from a service, a set of operations and a location for each operation compiled from a set of quantum computing instructions provided by a client device; (2) generating, by the driver node, a declarative instantiation plan for the set of operations identifying a plurality of worker nodes, each worker node corresponding to one of the locations; (3) instantiating, by the driver node, the declarative instantiation plan; (4) issuing, by the driver node, the operations to the worker nodes based on the locations for each operation; (5) receiving, by the driver node, results from each worker node; (6) aggregating, by the driver node, the results; and (7) returning, by the driver node, the aggregated results to the client device via the service.

The invention discloses a co-simulation method and device based on multiple simulators, and the method comprises the steps: integrating N simulators based on co-simulation middleware to carry out the co-simulation of a co-simulation task, and enabling the simulation co-simulation middleware to communicate with the simulators through a simulation agent, a corresponding simulation agent is needed for each simulation simulator; for each simulator, a simulation agent corresponding to each simulator is developed and completed in the co-simulation middleware in advance; in the co-simulation task execution process, an instruction needing to control the simulator and a result of the simulator are transmitted through the simulation agent; the co-simulation task is that the co-simulation middleware pushes a coupling simulation calculation process of the N simulators based on a preset simulation step length, and time synchronization is carried out based on a time axis of the co-simulation middleware. And after the collaborative simulation task is finished, data integration and cleaning are carried out.

The invention discloses a method for realizing accurate synchronization of a time sequence in a simulator based on a shared memory, which relates to the technical field of simulator development and cross-process communication, and comprises the following steps: constructing a standardized three-layer layout comprising a head control region, an annular data region and a compact storage unit, the annular data area circularly accesses, and the compact storage unit binds data and a time sequence; cross-platform zero-leakage resource management is realized through a global singleton handle manager, and interface multiplexing is provided or a shared memory is created and mapped; the sending end encodes data, binds a time sequence and atomically updates a write pointer, and the receiving end reads the data, calibrates the time sequence and atomically updates a read pointer; and executing time sequence precision, transmission delay, throughput and stability verification. According to the method, the lock competition overhead is eliminated, the cross-process data transmission efficiency is greatly improved, the time sequence synchronization accuracy is guaranteed, and the hardware bus refinement requirement is met.