282 results about "Simics" patented technology

The invention discloses a design method of a concept prototype of a flight control system, which belongs to the technical field of design of the control systems. The method comprises the following steps: step 1) carrying out demand analysis, management and confirmation on the flight control system; step 2) carrying out system analysis and confirmation on the flight control system, and carrying out structural and functional division on the system; step 3) designing all member simulators of the flight control system; and step 4) carrying out system level design and simulation on the flight control system, and establishing the concept prototype of the flight control system. The seamless butt joint between Rhapsody software and Matlab software can be realized by utilizing the point-to-point way, and design data in the two types of software can be organically combined. Compared with the prior art, by adopting the method, the correctness of the design of the flight control system from a top layer can be ensured, and the design efficiency of the whole flight control system can be greatly improved.

Systems and methods are provided for annotating software with performance information. The computer code is compiled into assembler code, the assembler code is translated into a simulation model, expressed in assembler-level source code. The simulation model is annotated with information for calculating various performance parameters of the software, such as timing information, or resource usage information. The simulation model is then re-compiled and executed on a simulator, optionally including a hardware simulation model, and the performance information is computed from the simulation.

The invention discloses a large-scale parallel program property-predication realizing method based on representative replay, belonging to the technical field of parallel program property prediction. The method comprises the following steps: collecting communication sequences and calculation vectors of parallel programs, analyzing calculation similarity of the processes, selecting a representativeprocess, recording the communication content of the representative process, using a calculation node of a target platform to replay the representative process, obtaining the sequence calculation timeof the representative process, and using the calculation time to replace the calculation time of other processes; obtaining the communication records of the parallel programs; and using a network simulator to automatically predict the final program property. By using the invention, only few hardware sources can be used, and the accurate parallel program property prediction can be obtained.

The invention relates to a programming language capable of cross-language reusing, and discloses a method for programming and developing software application programs by using a group of certain brief term and syntax rule with natural language semanteme. Through the description of multiple programming language families and the display method of the same thought realizing parts in multiple language development of certain software with an abstract special function, the cross-platform, cross-compiling, convertible and embeddable unified development is realized. Through the compiling tool disclosed by the invention, the same set of codes programmed by the language can be compiled into the applications with different states under different platforms; and the platform characteristics are realized by corresponding compiling tools. Through the converting tool disclosed by the tool, the codes programmed by the language can be converted into other languages as C++, Java, C#, Pascal and Obj-C, and can also be converted into the codes directly executed by the ARM embedded chip. Through the standard developing library disclosed by the invention, the language can be directly embedded into other languages for mixed programming. Through the IDE and the simulator disclosed by the invention, the cross-platform debugging and simulation can be realized.

The invention relates to a platform virtualization system comprising a CPU simulator, a memory virtualization module, and an external virtualization module. The CPU simulator reads an X86 architecture code instruction and judges whether an instruction basic block is translated or not; a binary translator is used for translation and comprises a translation engine and an execution engine; the translation engine translates an X86 architecture code into a Loongson platform code; the execution engine prepares the operational context of the Loongson platform code, locates the Loongson platform code corresponding to the X86 architecture code from a Loongson platform code cache and executes the code. The memory virtualization module uses a shadow page-table method. The external virtualization module establishes a corresponding device model for each external device. An X86 architecture virtual machine interacts with the external devices through the device models, thereby discovering and accessing the devices. The platform virtualization system allows information systems not matching with the domestic Loongson hardware platform yet to run in the domestic software-hardware environments in a virtualized manner, and contributions are made for the smooth transition between new and old technical systems in the automatic upgrading process of the information systems.

Abstract of the Disclosure 42Method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). Behavioral models of memories of simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e.g., Verilog). Simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. Structural models are stored for subsequent access during pattern generation. In another embodiment for modeling random access memories (RAMs), the ATPG memory primitives include memory primitives, data bus primitives, address bus primitives, read-port primitives and macro output primitives. In another embodiment for modeling content addressable memories (CAMs), the ATPG memory primitives include memory primitives, compare port primitives and macro output primitives. Functional equivalence between simplified behavioral models and simulation models can be verified with the same behavioral hardware description language simulator (e.g., Verilog). Another advantage is complicated memories, such as CAMs, can be accurately modeled for ATPG.

A system and method for measurement of the performance of a network by simulation, wherein time divergence is addressed by using discrete event simulation time to control and synchronize time advance or time slow down on virtual machines for large-scale hybrid network emulation, particularly where the loss of fidelity could otherwise be substantial. A dynamic time control and synchronization mechanism is implemented in a hypervisor clock control module on each test bed machine, which enables tight control of virtual machine time using time information from the simulation. A simulator state introspection and control module, running alongside the simulator, enables extraction of time information from the simulation and control of simulation time, which is supplied to the virtual machines. This is accomplished with a small footprint and low overhead.

A system for the development, compilation, execution, monitoring and debug of automated test and simulation systems in a flow chart programming language. A development and debug system, implemented as software on a computer, which provides an application developer the capability to enter fully defined application programs through the use of graphical flow charts. An executions system, implemented as a program on a device incorporating a central processing unit, memory, communications and necessary interfaces, which executes graphical flow charts compiled by the development and debug system. The development and debug system communicates with the execution system to download programs, control operation, monitor operation and provide a debugging environment.

The invention provides an analog input output method, a device and a system of virtual machine cluster. The analog input output method, the device and the system of the virtual machine cluster is suitable for the technical field of virtual machines. The analog input output method, the device and the system of the virtual machine cluster comprises that first servers receive analog input / output (I/O) processing instructions of a second server; the second server integrates all device models (DM) of virtual machines (VM) in a VM cluster; the I/O processing instructions are generated by the DMs; the first servers renew virtualization states of the VMs according to the analog I/O processing instructions, wherein the virtualization states of the VMs are instructed by the analog I/O processing instructions. In embodiments of the analog input output method, the device and the system of the virtual machine cluster, the communication between the servers of each VM and the server of each DM can be achieved by intensively operating the DMs of all VMs of the VM cluster on one server and utilizing a non-transparent bridge (NTB) mechanism of a peripheral component interconnect express (PCIE) or a remote direct memory access (RDMA). The analog I/O of the VM can be achieved and software architecture of the VM cluster is simplified efficiently. Using rate of the VM cluster resource can be improved.

The invention provides a Beidou global system soft and hard collaborative simulation test verification system. The Beidou global system soft and hard collaborative simulation test verification systemcomprises a software simulation unit, a hardware simulation unit, a software and hardware collaborative simulation control system, an environment simulation system and a time-frequency subsystem. Thesoftware simulation unit comprises a simulation model library, a simulation scheduling operation module, a scene configuration module, a monitoring and display module and a performance evaluation module. The hardware simulation unit comprises a hardware simulation system and an external interface system. The invention further provides an establishment method of the Beidou global system soft and hard collaborative simulation test verification system. The establishment method comprises the following steps of establishing the software simulation part, establishing the hardware simulation part, establishing the environment simulation subsystem, establishing the time frequency subsystem and establishing the software and hardware collaborative simulation control system; and performing test verification. Through the hardware simulator and the software model, the state of the Beidou engineering system can be approximated to the maximum extent, the number and the state of the test models can beflexibly configured, and butt joint verification with the real Beidou engineering system can be carried out.

A GUI placement information file in which the positions of GUIs are set as the ratio to the screen size and the sizes of the GUIs are set as fixed length is prepared in association with content. In a screen having such a screen size A that the GUIs do not overlap with each other even when the setting is obeyed, the respective GUIs are displayed with the positions and sizes in accordance with the setting of the GUI placement information file (screen 134). In a screen having such a screen size B that GUIs become a state of overlapping with each other when the setting is obeyed, the setting of the position of the relevant GUI is invalidated and the position is so decided that these GUIs abut on each other (screen 136). In the case of a screen having such a screen size C that a GUI becomes a state of running off the screen when the set sizes are obeyed even in the state in which the GUIs abut on each other, the sizes of the respective GUIs are reduced depending on the screen size and the GUIs are displayed in a packed manner (screen 138).

The invention discloses a method for realization and service for a trusted password module on an ARM platform. The method comprises following steps: firstly, receiving a trusted efficient agent located in a universal world and pre-processing a trusted service request from an application program, sending to the communication agent for forwarding the request and saving and switching to a working state of a main CPU core; then, receiving TCME of a trusted password module simulator and analyzing the forwarded request, initializing the CPU core according to the core number of CPUs of the platform and assigning all requests to TCME running in principal and subordinate CPUs for processing, wherein the TCME is used for providing standard trusted services according to single service request; and finally, supporting a password algorithm for TCME by a safety password library and providing protection by root keys stored in Secure Boot ROM. The method for realization and service for the trusted password module on the ARM platform has following advantages: efficiency of trusted service is improved when multiple cores are used for processing trusted service requests at the same time; and by utilizing a root key encryption projection safety password library for safety storage, safety of the password algorithm and secret keys is ensured.

The invention relates to an entity-based command authority simulation method and an entity-based command authority simulator. The entity-based command authority simulation method comprises the following steps of: 1, abstracting a command authority into a three-dimensional feature model; 2, determining the input parameters of the command authority; 3, calculating features of the command authority according to the input parameters of the command authority; and 4, outputting and displaying the features of the command authority. The method and the simulator can effectively support the design and optimization of the capability and behaviour of the command authority, reduce design and construction risks and improve the reliability and design level of design results.

The invention discloses a method for realizing cross compiling of a Docker mirror image. The method specifically comprises the following steps: S1, installing a qemu-user-static service program on a Docker mirror image cross compiling environment system, s2, checking whether a binfmt _ misc in the Linux system registers a corresponding simulator configuration or not; s3, determining the CPU architecture type of the Docker mirror image needing cross compiling, s4, a Docker file for constructing a Docker mirror image is compiled; docker mirror images of different target CPU frameworks are constructed by using the same Docker file, and the Docker mirror images of different target CPU frameworks are constructed by using the same Docker file. And S5, determining whether the generated Docker mirror image is the mirror image of the target CPU architecture or not by checking the identifier in the generated Docker mirror image. The invention relates to the technical field of computer programs.According to the method for realizing Docker mirror image cross compilation, when the application compilation environment is started, the difference of underlying hardware facilities can be completelyshielded, and the problem of cross-platform cross compilation is solved, so that the problem caused by the difference of underlying hardware can also be shielded while the application cross compilation environment is rapidly started.

The invention relates to an attack trapping system based on firmware simulation. The attack trapping system comprises the following steps: (1) obtaining and analyzing firmware; (2) for the firmware information obtained in the step (1), using a QEMU simulator to simulate target firmware through a system-level simulation technology; (3) on the basis of the step (2), constructing a honeypot system, deploying a high-interaction honeypot system based on an SSH proxy protocol in a virtualization environment, and performing information configuration; and (4) on the basis of the step (3), performing attack behavior capture, monitoring various attack behavior characteristics of the equipment in real time in the honeypot, and capturing information such as an attack initiating way of an attacker andthe like. According to the invention, analog simulation is carried out on the firmware through the QEMU simulator, and the honeypot environment based on the SSH protocol is deployed by using the virtualization technology, so that various attack behaviors for the equipment can be effectively monitored in real time, malicious attacks can be captured, and a more efficient and complete system securityprotection system can be constructed.

The invention discloses a universal configurable, compatible multi-model and domain-migratable multi-round dialogue system. The system comprises: a configurable module used for carrying out self-defined configuration according to professional knowledge of a current domain; a dialogue understanding module used for carrying out language coding on user statements through dialogue understanding, and carrying out intention recognition and joint extraction of slot value pairs by replacing a compatible dialogue understanding model; a dialogue state tracking module used for acquiring current multi-round historical dialogue state information; a strategy learning module used for performing action decision through the dialogue strategy model; a dialogue generation module used for generating dialoguesaccording to corresponding actions; and an online training module used for serving as a user simulator to be provided for developers, performing online iterative updating of the model and generatingavailable data. The whole architecture module of the system is universal, the system adapts to different application scenes, all field parameters are universal and configurable, corpora and dialogue understanding can be accepted at will, and a dialogue strategy model can be flexibly expanded and replaced.