105results about How to "Efficient debugging" patented technology

A debugging support method for object-oriented programs by which the debug target objects may be designated and a debugging support method equipped with various means for realizing said method. A first designation means (110) designates an object (100) as the debug target object. At a second designation means (101), a destination designation means (104) designates the destination of the event history and a range designation means (105) designates the range of objects targeted for debug support. While said designation is registered in a storage means (107), a second sending means (109) notifies a collection means (102) of the messages received by a receiving means (106) and messages sent by a first sending means (108). After the completion of the processes, a cancellation means (103) deletes the registered contents in said storage means (107).

The invention provides a self compensation floating swing arm independent suspension system, comprising a self compensation floating swing arm independent suspension device and a centrifugal force control scissors-type anti-roll bar device. The two mechanisms can be used in combination or independently and are applicable to both front wheels and rear wheels. The self compensation floating swing arm independent suspension system guarantees that wheels perform line bounce along a vertical direction of a car body on various kinds of road surfaces when a car runs at a low speed or at a high speed or makes turns and guarantees maximum contact area between the wheels and the road surfaces, with the parameters of king pin angle, toe-in angle, camber angle, wheel track, and axle base being maintained the same as original parameters; and, when the car makes turns, the centrifugal force control scissors-type anti-roll bar device works automatically, offsets a roll force with a force equal to the roll force in magnitude and opposite to the roll force in direction, and enables the car body to lower automatically, thereby improving anti-roll capacity and realizing idealization of controllability, safety, stability and comfort of the car. The self compensation floating swing arm independent suspension system has a simple structure, excellent performance, and low cost, and is easy to realize.

Disclosed are a debugging supporting apparatus, a debugging supporting method and its recording medium so constituted that even if an application developed in a simulation environment by OS simulator stops, OS control information can be referred to at that moment. The debugging supporting apparatus comprises a common file that is shared between the application and the OS debugger and which records common control information including the same data as item forming OS control information, writing means for writing specific item of the OS control information stored in the storage means on the common file as common control information, and reading means for reading out the common control information stored in the common file.

A method and system for query problem determination have been disclosed. The method includes receiving a database query; creating a query execution plan for the database query comprising a plurality of query plan operators; and executing the query execution plan, wherein a progress indicator is displayed for each query plan operator. The system includes a query progress monitor, which collects progress information for each query plan operator during the execution of the query execution plan. This progress information is then communicated to a query progress visualizer and a query progress analyzer, which graphically displays the progress information as a progress indicator for each query plan operator and performs debugger type operations, respectively. In this manner, information concerning the progress of the query execution is provided at a query operator level, such that the information may be used to more efficiently debug any problems with the query.

Large, complex SoCs comprise interconnections of various functional blocks, which blocks frequently running on different clock domains. By effectively controlling the clocks within the SoC, this invention provides a means to halt execution of a SoC and to then single or n-cycle step its execution in a real system environment. Accordingly, the invention provides an effective debugging tool to both the SoC designer and software designers whose code is executed by the SoC as it provides them the capability of studying the cause and effect of interactions between functional blocks. The invention is also applicable to SoCs containing only one functional block while containing complex circuitry operating on a clock different than the block's clock. In particular, the invention permits halting of the block clock and then single or n-cycle stepping its execution to permit analysis of the interactions between the block and the SoC circuitry.

A debugger display groups threads according to user-specified criteria. The threads may be grouped by type, by current or historic breakpoints, according to historical debug patterns, based on what thread spawned the thread, based on execution pattern, based on object class in a Java environment, based on Java thread group in a Java environment, or base on other suitable criteria. The grouping of threads is displayed graphically to a user of the debugger, thereby allowing more efficient debugging of multi-threaded computer programs.

A logic verification tool detects and flags a logic operation with high probability to cause a fault in an electronic system. An efficient logic debug method utilizes a partial sequence of signal outputs and state transitions to extrapolate a verification result with equivalent robustness to full regression testing.

To efficiently debug while reducing a debugging circuit in a system LSI made up of a plurality of CPUs.

A debugging apparatus includes debug object selection means 109 for selecting the CPU to be debugged from CPUs 11 and 12 in accordance with a debug object selection request from a host PC 15 connected to a system LSI 17, event information output means 110 for outputting internal event information of one selected CPU to be debugged, detected event storage means 106 for temporarily storing a detected event set by the host PC 15, and event comparison means 105 for making a comparison between the internal event information output from the event information output means 110 and the detected event stored in the detected event storage means 106 to detect a match therebetween. The event comparison means 105 notifies the host PC 15 that an event match is detected.

The invention discloses a camera online debugging method. A camera is arranged on a mobile terminal. The camera online debugging method includes the following steps: adding DRIVER_ATTR attributes in a camera bottom driving code at an android mobile terminal, and building document nodes; connecting a person computer (PC) with the mobile terminal through a universal serial bus (USB), switching the mobile terminal to an adb mode, opening the mobile terminal camera, and observing and testing camera image effect; selecting manufacturers and models of the camera at the PC end, and filling modified parameters; calling an adb program through the PC end, writing the switched parameters in the document nodes built in the mobile terminal through the USB, executing a store function of the DRIVER_ATTR attributes through the mobile terminal, and writing the parameters in the camera; contrasting and modifying repeatedly till results are satisfied; and storing the parameters. The camera online debugging method performs online real-time humanized and efficient debugging on the camera, can effectively improve camera debugging efficiency of the android system, and picks up best effect parameters conveniently.

To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.

A test process executed by a test system includes a test class thread for executing a test class in which a procedure for testing a device is described, and a tool thread for executing a tool which includes a function that can be used for the test of the device. Then, during debugging of the test class, the test system controls the test class thread so that the test class thread is in a stopped state, and controls the tool thread so that the tool thread is in an operating state.

A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

An installation comprises at least one sensor for providing sensor data representing a real system state of the installation and at least one actuator for acting on the real system state. A controller for controlling the installation comprises a data memory for storing the sensor data and a program memory for storing a machine code program. A programming tool for programming the controller includes a program editor, a debugging tool and a compiler. A machine code program is executed on the controller while the debugging tool is activated, and the debugging tool determines a reverse relationship between the machine code running on the controller and at least one high level control instruction shown in the program editor. The debugging tool reads sensor data from a data memory in the controller and assigns the sensor data to the at least one high level control instruction, thereby linking the at least one high level control instruction to a real system state during the execution of the machine code program.

The debug assisting apparatus comprises a task information recording device to record the execution information of task A, task B, and task C executed by the OS 1 in multitask processing, an object execution information recording device to record the information of the objects operated by the tasks, an information merging device both to chronologically merge the recorded object execution information and execution information of task A, task B, and task C and to store such information as the program operation history in a history storing device, and an output data generating device to generate the output data showing the execution progress of task A, task B, and task C and the operation of the objects in association according to the operation history table in the history storing device and output such data to the input/output device (monitor).

A high level synthesis device includes a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, capable of verifying a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

The embodiment of the present invention discloses an intelligent transformer substation secondary equipment panorama test system and a construction and test method thereof. According to the present invention, by analyzing a transformer substation database configuration file, all intelligent electronic devices and the configuration information of the intelligent electronic devices can be obtained, and by the virtual terminal input and output of the acquisition and control modules between the intelligent electronic devices, the connection between the intelligent electronic devices is realized; a secondary equipment panorama diagram is drawn by taking the intervals as units, the intelligent electronic devices in the panorama diagram are monitored real-timely, and the states and the data flow directions of the intelligent electronic device virtual terminals can be visualized; the connection states of the input and output virtual terminals of the intelligent electronic devices and the correlated devices are displayed, and the connection states of the virtual terminals and the information and the data flow directions of the devices of a transformer substation can be changed directly under the panorama diagram. The test system and the test method provided by the embodiment of the present invention can carry out the integration and visualization test on the functions of a plurality of intelligent electronic devices of the whole transformer substation simultaneously, thereby finishing the overall debugging and verification of the intelligent transformer substation secondary equipment efficiently and reliably.

The invention provides a bullet screen display method. The method comprises the following steps: obtaining bullet screen original data and bullet screen display parameters; adjusting the bullet screenoriginal data according to the bullet screen display parameters to generate corresponding bullet screen display data; and creating and displaying corresponding preview bullet screen according to thegenerated bullet screen display data. The invention further provides a bullet screen display data apparatus and a readable storage medium. During bullet screen debugging, the bullet screen display effect can be previewed in real time just by configuring the bullet screen display parameters.