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SPI verification platform based on UVM

A verification platform and verification environment technology, applied in the field of IP verification, can solve the problems of low verification efficiency, poor portability, difficult convergence of coverage, etc., and achieve the effect of accelerating coverage convergence, accelerating convergence, and easy reuse

Inactive Publication Date: 2021-03-09
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to provide a UVM-based SPI verification platform to solve the problem that the traditional verification method cannot cover all the function points to be verified well, the coverage rate is difficult to converge, the verification efficiency is low, and the portability is poor. Problems meeting large-scale design verification needs

Method used

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  • SPI verification platform based on UVM
  • SPI verification platform based on UVM

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Embodiment 1

[0029] In the present invention, a UVM-based SPI verification platform is proposed, and the UVM is used to build a module-level verification environment. Systemverilog is an excellent verification language, but it is obviously not enough to only use Systemverilog for verification, and the UVM verification methodology provides a basic class library and a basic verification structure, so as to quickly and efficiently build a verification platform. The verification platform proposed by the present invention is built based on UVM verification methodology and Systemverilog language, and constrained random excitation is applied to the SPI interface module, which can be reused in different environments and improves design verification efficiency.

[0030] The present invention uses the UVM verification methodology to build a function verification environment for the SPI module. SPI is the abbreviation of Serial Peripheral Interface (Serial Peripheral Interface), which has the charact...

test Embodiment t

[0031] Test case testcase: test stimulus for the entire verification platform.

[0032] Basic test base_test: start the test, all testcases in the platform inherit from base_test.

[0033] Authentication environment env: used for the instantiation and management of various components.

[0034] Driver driver: used to apply excitation and data conversion to the dut port of the design under test.

[0035] Monitor monitor: used to collect the data of the dut port and perform data conversion.

[0036] Transaction transaction: used to define the basic item data package.

[0037] Sequence generator sequence: used to generate transaction transaction.

[0038] Sequence management sequencer: used to manage the sequence and generate a valid sequence sequence.

[0039]Agent agent: used for encapsulation and instantiation of driver, monitor and sequencer.

[0040] Scoreboard scoreboard: used to compare the output data of the dut port with the expected value after the stimulus is appli...

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Abstract

The invention discloses an SPI verification platform based on a UVM, and belongs to the field of IP verification in integrated circuit design. According to the method for building the module-level reusable verification environment, the connection mode of all components in the verification environment is explained, the definition format of the transaction-level SPI data is given, test cases can beconveniently built in the built verification environment, and convergence of the coverage rate is accelerated. According to the method, the latest UVM verification methodology and the SystemVerilog language are adopted to build a verification environment; the proposed UVM verification environment is concise and expandable, high in portability and easy to reuse; various test scenes can be flexiblyconstructed, constrained random excitation is added, and coverage rate convergence is accelerated.

Description

technical field [0001] The invention relates to the technical field of IP verification in integrated circuit design, in particular to a UVM-based SPI verification platform. Background technique [0002] With the continuous expansion of SoC design and FPGA design scale, more and more IP modules are integrated in the SoC chip, and its functions are becoming larger and larger, the development cycle of the chip is getting longer and longer, and the construction of the verification platform is also more complicated. Chip verification plays a vital role in the entire SoC design. In today's mainstream integrated circuit design companies, verification accounts for as much as 70% of the entire chip development cycle. The traditional chip verification method can no longer meet the requirements. The verification requirements of today's large-scale IC chip design. The traditional verification environment is built based on the Verilog language, and the directional test stimulus is writt...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F13/42
CPCG06F11/221G06F11/2273G06F13/4282
Inventor 桂江华殷庆会王凯董利
Owner 58TH RES INST OF CETC
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