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Universal variable constraint signal randomizing method

A constrained signal and variable technology, applied in the field of signal randomness, can solve problems such as code redundancy, improve work efficiency, achieve simple and convenient implementation, and reduce the amount of code

Pending Publication Date: 2020-04-10
SHANDONG SINOCHIP SEMICON
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Problems solved by technology

[0002] When verifying chips with complex control functions, there will be complex constraint relationships between control signals. At the same time, the control signals of the previous configuration may affect the randomness of the current control signal, that is, the previous configuration will become the random constraint of this configuration, often In the case of random constraint changes, the general approach is to write constraint relationship program codes in the program randomly for each control signal. There will be different program blocks between different signals, that is, different constraint programs. In this way, there will be program Repetition on the Internet, resulting in code redundancy

Method used

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  • Universal variable constraint signal randomizing method

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Embodiment 1

[0013] This embodiment discloses a general variable constraint signal randomization method, such as figure 1 shown, including the following steps:

[0014] S01), constraint input, use the four-valued variables in the SystemVerilog language to represent the constraint relationship between random signals, each variable represents a one-bit wide control signal, arranged from left to right to form a multi-bit variable, a A multi-bit variable represents a constraint relationship, and multiple constraint relationships can be entered. The position of the control signal corresponds to the position of the multi-bit variable. The priority of the control signal is arranged from high to low, and the high priority variable determines the low priority variable. value of . The four-valued variable has four values ​​of 1, 0, x, and z. In this method, three values ​​are used, namely 1, 0, and x. The value of a bit in the constraint variable means that the value of the variable is 1. A bit of...

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Abstract

The invention discloses a universal variable constraint signal randomizing method. According to the method, a four-value variable in a SystemVerilog language is used for representing a constraint relation between signals, the constraint relation is transmitted into a program block through a program interface, the program block analyzes the constraint, and a random variable value meeting the constraint relation is randomly obtained according to the constraint. When control signals with different constraint relations are randomized, the randomization operation of the signals can be simply and conveniently finished under the condition of not increasing codes. The method is simple and convenient to implement, random signals with different constraints are randomized by using one program block,corresponding constraint program codes do not need to be written for different constraint relationships, a code quantity is reduced, and working efficiency is improved.

Description

technical field [0001] The invention relates to a signal randomization method, in particular to a general variable constraint signal randomization method. Background technique [0002] When verifying chips with complex control functions, there will be complex constraints between control signals, and the control signals of the previous configuration may affect the randomness of the current control signals, that is, the previous configuration will become the constraint of the random configuration of this time, often In the case of random constraint changes, the general practice is to write the constraint relationship program code in the program randomly for each control signal. There will be different program blocks between different signals, that is, different constraint programs. This way, there will be programs. The duplication of the code, resulting in code redundancy. SUMMARY OF THE INVENTION [0003] In view of the defects of the prior art, the present invention provi...

Claims

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Application Information

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IPC IPC(8): G06F11/263
CPCG06F11/263
Inventor 李文军李风志戴绍新姚香君石易明
Owner SHANDONG SINOCHIP SEMICON
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