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Method and device for automatically generating assertion

An automatic generation and template technology, applied in the field of verification, can solve problems such as project delay and long development cycle, and achieve the effect of reducing the difficulty of use and ensuring the progress of the project

Active Publication Date: 2013-04-03
青岛中星微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Since each development project has a certain time limit requirement, as the Assertion code needs to be written by technicians who are familiar with SVA (SystemVerilog Assertion) syntax, and the development cycle is long, when the project pressure is high, the project will be delayed

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  • Method and device for automatically generating assertion

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Embodiment Construction

[0049] In the method and device for automatically generating an assertion in the embodiment of the present invention, a plurality of assertion templates and corresponding assertion verification codes are set in advance, and then the waveform information of the object to be verified is extracted from the simulation waveform data, and the waveform information that matches the waveform information The assertion verification code corresponding to the assertion template is used as the assertion verification code of the module to be verified, which reduces the difficulty of using the Assertion (assertion) code in the project development process and ensures the progress of the project.

[0050] A method for automatically generating assertions in an embodiment of the present invention is used to generate assertion verification codes for a module to be verified, such as figure 1 Shown include:

[0051] The determining step 11 is used to determine the simulation waveform data correspond...

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Abstract

The invention discloses a method and device for automatically generating an assertion. The method is used for generating an assertion verification code for a to-be-verified module, and comprises the steps as follows: determining simulation waveform data, a to-be-verified object and a waveform data extraction condition corresponding to the to-be-verified module according to user input; extracting a part of the simulation waveform data meeting the waveform extraction condition from the simulation waveform data of the to-be-verified object as to-be-matched waveform data; calculating the value of the to-be-verified object according to the to-be-matched waveform data; selecting at least one assertion template matched with the value of the to-be-verified object from a plurality of pre-stored assertion modules; and outputting an SVA (SystemVerilog Assertion) code corresponding to the selected assertion module as the assertion verification code of the to-be-verified module. According to the method, the using difficulty of the assertion code in the project development process is lowered and the project progress is guaranteed.

Description

technical field [0001] The invention relates to the technical field of verification, in particular to a method and device for automatically generating assertions. Background technique [0002] At present, SoC (System on Chip, system-on-chip / system-on-chip) is becoming more and more complex, and simulation verification is becoming more and more difficult. [0003] The verification based on Assertion (assertion) is paid more and more attention as an important verification. [0004] However, Assertion-based verification has at least the following disadvantages: [0005] Since each development project has a certain time limit requirement, as the Assertion code needs to be written by technicians who are familiar with SVA (SystemVerilog Assertion) syntax, and the development cycle is long, when the project pressure is high, the project will be delayed. Contents of the invention [0006] The purpose of the embodiments of the present invention is to provide a method and device f...

Claims

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Application Information

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IPC IPC(8): G06F9/44
Inventor 徐林伟王欣
Owner 青岛中星微电子有限公司
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