Efficient digital circuit algorithm verification device

Abstract

The invention provides an efficient digital circuit algorithm verification device in order to improve complexity and low efficiency in algorithm verification of a digital circuit. The verification platform is combined with a systemverilog verification language, an algorithm tool Matlab and an automatic running script Python, so that the algorithm verification becomes intelligent and efficient.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit chip design. In particular, it relates to a chip verification system and method. Background technique [0002] What is the goal of chip verification? If you think "found a bug", you're only partially right. The goal of verification is to ensure that the chip has been designed to a specific set of functions according to the design specification. That is, whether the design has accurately reflected the design specification. [0003] Verifiers face different verification requirements depending on the project. Therefore, different verification methods need to be adopted to realize the verification model. Whether you build a verification platform with simple verilog or use complex UVM methodology, it is not simply to enter the stimulus and confirm the design is correct by simply checking the waveform output. [0004] Aiming at the algorithm verification method, the present invention ex...

AI Technical Summary

Problems solved by technology

Verification engineers need to check the waveform files generated by the environment to confirm whether the intermediate steps of the DUT are correct during the entire operation process. Not only that, a large number of tests have brought a lot of annoyance in writing test cases, and each large number of calculations will bring a lot of trouble to the verification engineer. A lot of headaches... all kinds of disadvantages will not be repeated one by one

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