BFM (Bus Function Model)-based method for SystemVerilog to build protocol verification platform

A verification platform and protocol technology, applied in the computer field, can solve problems such as difficult protocol conversion verification, long time-consuming, difficult debugging, etc., and achieve the effect of simplifying the protocol processing process and increasing throughput

Active Publication Date: 2016-09-07
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the docking verification between the two protocols is verified after the RTL source code design is completed, it will take a long time to build a verification platform using the traditional verification method of Verilog, and because the source code design involves parity check, ECC, limited storage resources and For various functions such as credit issues, it is difficult to debug when problems occur, and it is difficult to conduct special verification for protocol conversion, so it is difficult to guarantee the completeness of protocol conversion verification
With the increase of design complexity and protocol complexity, traditional verification methods will bring greater difficulty to the verification work

Method used

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  • BFM (Bus Function Model)-based method for SystemVerilog to build protocol verification platform

Examples

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Effect test

Embodiment 1

[0025] Such as figure 1 As shown, a method of building a protocol verification platform based on SystemVerilog of BFM, the method utilizes the support characteristics of SystemVerilog for verification, and perfectly supports the realization of protocol conversion and consistency. The implementation process is as follows:

[0026] (1) Build a Transceiver, responsible for sending and receiving, dismantling / assembling Class A protocol messages;

[0027] (2) Build the Catalog directory structure and be responsible for the recording of consistent information;

[0028] (3) Realize the protocol table model, responsible for realizing protocol conversion;

[0029] (4) Build Handler, responsible for protocol processing.

Embodiment 2

[0031] On the basis of Embodiment 1, the method described in this embodiment simulates multi-Clumps communication through BFM, and sends a type A protocol message.

Embodiment 3

[0033] On the basis of Embodiment 1 or 2, the Transceiver described in this embodiment receives and sends the Class A protocol message through the DPI interface, completes the splitting of the protocol message packet, sends it to the Handler for processing, and receives the Handler processing result to assemble into a The type A message packet is sent out.

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Abstract

The invention discloses a BFM (Bus Function Model)-based method for SystemVerilog to build a protocol verification platform. The method comprises the following implementation process: building a Transceiver which is in charge of transceiving and disassembling / assembling an A-class protocol message; building a Catalog structure which is in charge of recording consistency information; realizing a protocol table model which is in charge of realizing protocol conversion; and building a Handler which is in charge of processing the protocol. The method simplifies a protocol processing process, adopts a one-by-one way, does not relate to a resource dispatching problem, improves protocol conversion communication among multiple clumps, and fully utilizes the verification characteristics of sv, the handling capacity of the protocol message is enlarged by a queue and a dynamic associative array, the Catalog structure is visible on the whole platform, and communication between the Transceiver and the BFM adopts a simple DPI interface.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a method for building a protocol verification platform based on BFM SystemVerilog. Background technique [0002] In a multi-clumps system, the chip responsible for the communication between CPUs in each clump needs to maintain the data consistency between each CPU. When designing a chip, the CPU has its own protocol inside, but when communicating between different clumps, it often designs its own inter-domain protocol for the sake of data security and transmission efficiency. At this time, it will be designed to The docking problem between the two protocols. If the docking verification between the two protocols is verified after the RTL source code design is completed, it will take a long time to build a verification platform using the traditional verification method of Verilog, and because the source code design involves parity check, ECC, limited storage resources and For v...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163
CPCG06F15/163
Inventor 张永照童元满李仁刚
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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