41 results about "Associative array" patented technology

This invention relates to a method and processor (19) for power analysis in digital circuits. The method incorporates a main processor (19) and an associative memory mechanism (101a, 101b, 102, 104, 105, 106), the associative memory mechanism comprising a plurality of associative arrays (101a, 101b), an input value register (102), at least one result register (104) and a memory block area (29). A circuit design is transformed into a functionally equivalent model format suitable for processing in the associative array and thereafter input vectors are applied to the circuit and a record is kept of the inputs and or the outputs on each of the gates in the circuit over a specified time period. In this way, it is possible to calculate the leakage power dissipation as well as both the toggle dynamic power and the transition dynamic power.

A method is provided for compressing data from a stream of values using one or many distinct memory addresses as workspace, each memory address containing one or many values. The method works by reading two contiguous data values, of length K and N bits, from the stream, as a memory address reference (MAR) and a symbol, respectively. If the symbol does not match any of the values in the memory address pointed to by MAR, the symbol replaces one of those values, and a MISS code, followed by the symbol, is appended to the compressed stream; otherwise, a HIT code is appended to the compressed stream, said code representing a function of the location where the matched value was found in the memory address. Advantageously, the workspace behaves analogous to a cache memory used in computer architecture, allowing hardware or software parallel implementations using content addressable memory or associative arrays.

A method for providing symbolic access to a plurality of objects stored in a data storage is provided. An associative array comprising a plurality of associative array keys and a plurality of associative array values may be generated. A data array comprising a plurality of data array elements may be generated, such that each object stores a sortable property value of the object and an original offset of the object. A mapping table to map original offsets to modified offsets is generated. The mapping table includes a plurality of mapping table elements, and each associative array value is used as an offset into the mapping table, and each mapping table element storing a modified offset, each modified offset is a numeric value used as an offset into the data array.

Systems and methods are provided to track the state of a data forwarding component, such as a USB transaction translator, included in a downstream hub within a multi-speed bus environment. The data forwarding component accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction, performing a lookup in an associative array using hub-specific information provided in the split packet request to determine whether an identifier is allocated to the data forwarding component, and if it is determined, based on the lookup, that an identifier is allocated to the data forwarding component, storing state information associated with the split packet request. The associative array may include multiple identifiers, each of which has an associated state field configured to track information, such as the number of packets-in-progress and bytes-in-progress to a particular data forwarding component.

An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.

A structured document expansion method converted a structured document into a format enabling easy manipulation by an application. A structured document is expanded into a format for easy manipulation without requiring complex knowledge. A two-stage associative array structure is adopted to enable easy manipulation of various types of data spanning the entire structured document merely through intuitive array operations, and both associative arrays are linked by sequence numbers. The latter-stage associative array can be accessed from the former-stage associative array using element names, and in addition, the latter stage can be made a two-dimensional associative array to represent hierarchical levels.

A method for transforming a plurality of random biological sequence data to an ordered biological data sequence, the method comprises reading a reference biological data sequence; generating a plurality of indexes based on the reference biological data sequence; generating a library, the library including the plurality of indexes; organizing the library into an associative array; reading the plurality of random biological sequence data; encoding the plurality of random biological sequence data; comparing the encoded plurality of random biological sequence data to the reference biological sequence; and aligning the encoded plurality of random biological sequence data to the reference biological sequence using an alignment algorithm to generate a plurality of alignment data.

A method is provided for compressing data from a stream of values using one or many distinct memory addresses as workspace, each memory address containing one or many values. The method works by reading two contiguous data values, of length K and N bits, from the stream, as a memory address reference (MAR) and a symbol, respectively. If the symbol does not match any of the values in the memory address pointed to by MAR, the symbol replaces one of those values, and a MISS code, followed by the symbol, is appended to the compressed stream; otherwise, a HIT code is appended to the compressed stream, said code representing a function of the location where the matched value was found in the memory address. Advantageously, the workspace behaves analogous to a cache memory used in computer architecture, allowing hardware or software parallel implementations using content addressable memory or associative arrays.

The invention performs the following steps: segmenting a power transmission tower, determining the local serial number of a connection point associated with each component and the serial number of thecomponent cross section in each segment in a segment-by-segment mode, determining the local serial number of a reference point according to the connection point and an angle steel component sectionaldirection designation principle, further generating an associative array of the component and the connection point, generating a modeling file of a finite element model of the power transmission tower, and establishing the finite element model of the power transmission tower. Since the modeling file of the invention includes the overall serial number of the connection point, the overall serial number of the reference point, the serial number of the component cross section, a connection point coordinate and a reference point coordinate, the direction of the cross section of an angle steel component can be quickly and correctly determined according to the reference point, the model can be ensured to be closer to a prototype, and the technical problem that a traditional modeling technique cannot quickly and correctly determine the direction of the cross section of the angle steel component can be solved.

A method and a processor for parallel processing of logic event simulation on circuits comprising a polarity of logic gates, the logic gates having interconnect lines therebetween, the processor (1) further comprising a main processor (2) and an associative memory mechanism (3), the associative memory mechanism (3) comprising a plurality of associative arrays (5, 6) and at least one result register, and there is provided accessible external memory (4) in which a circuit representation may be stored and divided into a plurality of segments, each of the segments having a segment identifier, which in turn has segment data associated therewith. The segment identifier and segment data being stored in a segment table (14) in the associative memory mechanism. Each of the segments may then be brought into the associative memory mechanism (3) for evaluation one at a time. There is additionally provided an amended result registering mechanism (8) to allow numerous tests and gate pairs to be carried out and recorded.

A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction / invalidation of the region previously evicted from the RCA.

The invention discloses a floating display method, a virtual reality device and a storage medium. The method includes the following steps: when a virtual reality device plays a panoramic video, acquiring the current playback time of the panoramic video and the current viewing angle of users; determining whether there is an associative array composed of the current playback time and the current viewing angle in a preset floating display information list; and if there is an associative array in the floating display information list, calling corresponding display content from the floating display information list according to the associative array, and displaying the display content on the current playback interface. The current playback time and the current viewing angle are acquired in real time, and whether the current playback time and the current viewing angle conform to a preset display rule is determined. If the current playback time and the current viewing angle conform to the preset display rule, a floating window is popped up to display content associated with the current video, in order to extend the content of the current video and make it more interesting for users to watch a panoramic video.

The invention discloses a universal communication protocol processing method, comprising the following steps that S1, a universal communication protocol processing system is established; S2, an establishment module establishes a universal XML protocol file comprising all communication protocols; S3, an associative array obtaining module loads the universal XML protocol file into a two-dimensionalassociative array of a C++ standard template base, thereby obtaining an associative array comprising the universal XML protocol file; and S4, after an application program receives communication data,a universal communication protocol read module selects corresponding protocols in the associative array according to message headers of the communication data, hexadecimal values of words are obtainedaccording to start / end bytes and start / end bits of the words in the corresponding protocols, and practical values of the words are obtained according to types of the communication data, thereby finishing universal communication protocol processing. According to the method, an intermediate link of paper protocols is cancelled, a protocol analysis error rate can be effectively reduced, the manpowerand time cost is reduced, and moreover, application program architecture is prevented from being bloated.

The invention provides a verification method of processor random instruction reusability. The verification method includes: running a reference model and reading a binary iss.vmem instruction file into an associative array dut_mem and iss_mem; when the address, of instructions or the associative array of the reference model does not exist, randomly generating the instructions or data and respectively filling the instructions or data into the dut_mem and the iss_mem; running a processor, reading mem_dut through an external slave memory model, and when a non-existing address is read by the processor, filling in the dut_mem with random instructions continuously; after running of the processor is completed, writing the dut_mem into dut.mem, and storing the address of the dut_mem and corresponding data; reading the dut.mem to execute the next running of the processor. With the method, the instructions and the data that truly needed by the processor can be generated randomly, and good reusability is achieved.

The invention provides a format data flow file loading mode. A format data flow file is stored in a server. The server cuts the format data flow file into a plurality of independent files. Each independent file contains a code and a page number. A method for loading the format data flow file to a device terminal comprises the steps of creating an association array, wherein the association array contains file sequence association and file page number association, wherein the file sequence association is obtained by the independent files according to code sorting, and the file page number association is obtained by the corresponding independent file page numbers in the file sequence association; calculating a page number sum of the independent files, performing rendering by the device terminal to obtain a file frame, and performing downloading by multiple threads to obtain the format data flow file; and according to the page number of the current page of the format data flow file, obtaining the corresponding independent file page number, calculating the page numbers of first P pages and last Q pages of the page, and performing rendering by the device terminal. According to the loading mode, the file loading speed can be increased, and the format data flow file can be viewed without waiting until the format data flow file is completely downloaded, so that the synthesis step of the server is removed and the running burden is reduced.

A scheduler for a server includes a timestamp associative array for storing timestamps. The scheduler includes an advanced elastic time recovery mechanism having a processor in communication with the associative array which uses a wildcard search to find at least one timestamp in the associative array to schedule for service by the server in a single search, and to increment operational time by more than 1 in a given clock cycle. A method of using a scheduler for a server includes the steps of storing timestamps in a timestamp associative array. There is the step of using a wildcard search of an advanced elastic time recovery mechanism having a processor in communication with the associative array to find a timestamp in the associative array to schedule for service by the server in a single search. There is the step of incrementing operational time by more than 1 in a given clock cycle.

An apparatus for servicing connections in a telecommunications network comprises N ports in communication with the connections through the network. Each port supporting a plurality of virtual links, and each virtual link supporting a plurality of rate groups. The apparatus comprises a processor for providing service to the connections. The apparatus comprises an associative array that stores timestamps of the virtual links and the rate groups. The apparatus comprises a scheduler which chooses which virtual link and rate group is to receive service from the processor as a function of a timestamp. An apparatus for servicing connections in a telecommunications network. The apparatus comprises N ports in communication with the connections through the network. Each port supporting a plurality of virtual links, and each virtual link supporting a plurality of rate groups. The apparatus comprises a processor for providing service to the connections. The apparatus comprises a memory that stores timestamps of the virtual links and the rate groups. The apparatus comprises a scheduler which chooses which virtual link and rate group is to receive service from the processor as a function of a timestamp by searching the timestamps while the timestamps are stored in the memory. A method for servicing connections in a telecommunications network.

The invention discloses a BFM (Bus Function Model)-based method for SystemVerilog to build a protocol verification platform. The method comprises the following implementation process: building a Transceiver which is in charge of transceiving and disassembling / assembling an A-class protocol message; building a Catalog structure which is in charge of recording consistency information; realizing a protocol table model which is in charge of realizing protocol conversion; and building a Handler which is in charge of processing the protocol. The method simplifies a protocol processing process, adopts a one-by-one way, does not relate to a resource dispatching problem, improves protocol conversion communication among multiple clumps, and fully utilizes the verification characteristics of sv, the handling capacity of the protocol message is enlarged by a queue and a dynamic associative array, the Catalog structure is visible on the whole platform, and communication between the Transceiver and the BFM adopts a simple DPI interface.

A display system includes a display panel, a solar battery, an electric current measuring module, a memory, and a brightness adjusting module. The solar battery is for converting light energy into electric current. The electric current measuring module is for measuring electric current generated from the solar battery. The memory is for storing a pre-defined associative array of current values and their corresponding brightness values. The brightness adjusting module is for querying the associative array stored in the memory to get the corresponding brightness value, using the measured electric current value as a key, and adjusting the brightness of the display based on the brightness value returned from the associative array.

The invention provides an anti-fake system for fireworks and crackers based on a dot-matrix graph, and the system comprises a dot-matrix graph generation module which is used for generating the dot-matrix graph with a logic relation; a dot-matrix graph database which is used for storing the dot-matrix graph with the logic relation; a dot-matrix graph transmitting module which is used for enabling the dot-matrix graph to be transmitted to an external packaging printing end; a dot-matrix graph printing module which is used for printing the dot-matrix graph on each external package of the same batch, wherein one dot-matrix graph is just corresponding to the external package of one batch and the products of one batch; a correlation database which is used for carrying out the information binding of the dot-matrix graph, the external package and the products, forming a correlation array and storing the correlation array; and a cloud server which is used for storing the correlation array at a cloud side. According to the invention, the external packages of fireworks are printed with the dot-matrix graphs and two-dimensional codes for achieving fake prevention and tracing, and the system enables the producer, certificate, circulating and storage information of products to be able to be traced in the whole process, thereby facilitating the supervision and guaranteeing the safety of people's lives and properties.

The invention discloses a stamp album information management method based on a 2 dimensional code. The method includes the following steps: generating and storing an initial 2 dimensional code; printing the initial 2 dimensional code on a predetermined position of a stamp album; analyzing the initial 2 dimensional code and redefining the content of the 2 dimensional code so as to generate a self-defined 2 dimensional code which includes the index information of the stamp album; binding the self-defined 2 dimensional code to the index information to form an associative array and store the associative array; and uploading the associative array to a cloud server. The index information includes the types, themes, numbers, issuing years and other basic information of the stamps contained in the stamp album. The method assigns the 2 dimensional code to the stamp album, and redefines the 2 dimensional code so as to contain the index information of the stamp album, so that when it is needed to find a certain stamp album or a certain stamp in the stamp album, a user does not need to browse the stamp albums one by one, and can check the index information by scanning the 2 dimensional code to learn of substantial content. Therefore, the method can provide content indexing for the stamp albums and provide convenience for follow up indexing.

Implementations of the present specification provide a method and an apparatus for grouping transactions in a blockchain. The method includes: obtaining a first transaction in multiple transactions; obtaining a first variable accessed in the first transaction; reading a first value of a first belonging variable corresponding to the first variable; reading a first value of a first associated variable corresponding to the first transaction; if the first value of the first belonging variable is a numbering value of a second transaction in the multiple transactions, recording an association relationship between the first transaction and the second transaction in the associative array by performing an atomic comparative change operation on an atomic variable in an associative array; and grouping the multiple transactions based on the associative array.

A system and method for cybersecurity reconnaissance, analysis, and scoring that uses distributed, cloud-based computing services to provide sufficient scalability for analysis of enterprise IT networks using only publicly available characterizations. The system and method comprise an in-memory associative array which manages a queue of vulnerability search tasks through a public-facing proxy network. The public-facing proxy network has search nodes configurable to present the network to search tools in a desired manner to control certain aspects of the search to obtain the desired results. A distributed data processing engine and cloud-based storage are used to provide scalable computing power and storage. Each of the cloud-based computing services is containerized and orchestrated for management and efficient scaling purposes.

The invention provides an autograph album information management method based on a two-dimensional code, and the method comprises the steps: generating and storing an initial two-dimensional code; enabling the initial two-dimensional code to be printed at a preset position of an autograph album; carrying out the analysis and content redefining of the initial two-dimensional code, so as to generate a customized two-dimensional code, wherein the customized two-dimensional code comprises the brief introduction information of the autograph album; enabling the customized two-dimensional code to be bound with the brief introduction information, and forming and storing a correlation array; and uploading the correlation array to a cloud server, wherein the brief introduction information comprises at least one of the following parts: the type of the autograph album, involved events, time section, place and content. Through adding the two-dimensional code to the autograph album, the method carries out the customization of the two-dimensional code, so as to enable the two-dimensional code to be embedded in the brief introduction information of the autograph album. When one autograph or one picture is needed, there is no need to check pages one by one, and even no need to take out the autograph album from a bookcase. The main content can be obtained through scanning the two-dimensional code, thereby providing a content index for the autograph album, and bringing convenience to users for subsequent look-up.

The invention provides a two-dimensional code-based monitoring information management method, comprising: generating and storing an initial two-dimensional code; sending the initial two-dimensional code to a wearable product manufacturer; printing the initial two-dimensional code on the wearable product; After consumers purchase the wearable product, the initial QR code on it is parsed and the content redefines to generate a custom QR code, the custom QR code contains monitoring information; the custom QR code and the monitoring information are combined. Binding, forming an associative array and storing; uploading the associative array to the cloud server, wherein the guardianship information includes at least one guardian information and at least one guardian information. The invention embeds the guardianship information into the custom two-dimensional code. When the child is lost, passers-by can read the relevant information of the guardian by scanning and analyzing the two-dimensional code, get in touch in time, make full use of social goodwill resources, and provide accurate and accurate information feedback. The QR code is valid for a long time and is more secure and reliable.