Communication interface method of processor reference model under multiple simulation and verification platforms

Abstract

The invention relates to a communication interface method of a processor reference model under multiple simulation and verification platforms, wherein the communication interface method is used for realizing a blockable communication interface between the processor reference model and the verification platforms. The communication interface method comprises the steps of: under a VCS (Verilog Compiler Simulator) simulation and verification platform, defining a transaction-level communication interface according to an interface requirement of the processor reference model, fulfilling the function of a defined interface function to realize the interaction with the processor reference model, compiling an interface definition file and generating a corresponding SystemC / SystemVerilog adapter by using a VCS tool command, and exporting an interface performance function of a subsequent adapter to SystemVerilog by using a DPI (Direct Programming Interface); and under a Questa / Ncsim simulation platform, constructing a SystemC module, defining a member function, exporting a macro interface function embedded in a simulation tool to verilog, and importing the interface function by using an import sentence in the verilog.

Description

technical field [0001] The invention relates to the technical field of processor verification, in particular to an interface communication method suitable for a processor reference model described by SystemC under a multi-simulation platform and Testbench. Background technique [0002] With the continuous emergence of new integrated circuit verification languages, the use of advanced verification languages ​​and verification methodologies can greatly improve the efficiency of chip verification. System C is a software / hardware co-design language, a new system-level modeling language. SystemC is formed by extending the hardware class and simulation core on the basis of C++. Due to the combination of the advantages of object-oriented programming and hardware modeling mechanism principles, SystemC can carry out system design at different levels of abstraction. The hardware part of the system can be described by the SystemC class, and its basic unit is the module. The module can...

AI Technical Summary

Problems solved by technology

[0017] The present invention overcomes the shortcomings of the traditional verification environment, builds an efficient coverage-driven constrained random verification environment, and verifies whether the characteristics of the processor are consistent with those of the reference model, so it is necessary to solve the communication between the processor reference model and the verification platform

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