AHB core random verification method based on systemverilog
A random verification and mainframe technology, applied in instruments, electrical digital data processing, computing, etc., can solve problems such as bloat, loose relationship between test items, and failure to consider the mixing of multiple emergencies, etc., to achieve a complete test process , the effect of improving speed and completeness
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[0025] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.
[0026] The IP to be detected is the AHB bus IP, so the verification method must be able to generate a feedback signal and update the input according to the feedback signal. Therefore, the required verification environment needs to be able to process these feedback signals and adjust the verification conditions in real time to check whether these feedbacks and the changes in the input conditions caused by the feedback are in compliance with the protocol.
[0027] figure 1 It schematically shows the flowchart of the AHB core random verification method based on systemverilog according to a preferred embodiment of the present invention. figure 2 It schematically shows a block diagram of a systemverilog-based AHB core random verification method acc...
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