A random verification method of ahb kernel based on systemverilog

A random verification, host technology, applied in the direction of instrumentation, error detection/correction, calculation, etc., can solve problems such as bloat, test items are not closely related, and cannot take into account the mixing of multiple emergencies, so as to improve speed and Completeness, the effect of a complete testing process

Active Publication Date: 2019-06-28
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0004] The traditional verification method is too bloated for a complete verification of a protocol. How many test items need to be tested depends entirely on the personal level of the engineer in charge, and the relationship between each test item is not close, and it is often impossible to consider multiple emergencies. Mixed situations, or the need to expand the test item library to meet the completeness

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  • A random verification method of ahb kernel based on systemverilog
  • A random verification method of ahb kernel based on systemverilog

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Embodiment Construction

[0025] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0026] The IP to be detected is the AHB bus IP, so the verification method must be able to generate a feedback signal and update the input according to the feedback signal. Therefore, the required verification environment needs to be able to process these feedback signals and adjust the verification conditions in real time to check whether these feedbacks and the changes in the input conditions caused by the feedback are in compliance with the protocol.

[0027] figure 1 It schematically shows the flowchart of the AHB core random verification method based on systemverilog according to a preferred embodiment of the present invention. figure 2 It schematically shows a block diagram of a systemverilog-based AHB core random verification method acc...

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Abstract

The invention provides an AHB core random verification method based on systemverilog. The method comprises the following steps: reading data of an excitation generating module at the beginning of each period by use of an excitation driving module, and transmitting the data to a to-be-tested IP module; feeding back the data of a slave in the excitation driving module to a host of the excitation generating module at the end of the period by use of a feedback signal collecting module; restraining an allowable input kind list of a next period according to the data provided by the feedback signal collecting module by use of the excitation generating module, and randomly selecting one kind from the allowable input kind list at the beginning of the next period; collecting input-output information of the to-be-tested IP at each period by use of a monitoring check module, printing the input-output information to log, and then checking whether the input-output information meets an assertion requirement; directly comparing whether the judgment meets the requirement of a predetermined protocol according to the state of the IP at a predetermined moment by use of an assertion module.

Description

technical field [0001] The present invention relates to the field of digital IP (intellectual property module) verification environment construction, in particular to random vector constraints based on systemverilog, and automatic comparative analysis of test results; more specifically, the present invention relates to a systemverilog-based AHB nuclear random verification method. Background technique [0002] The traditional verification method relies on writing different test items (test patterns), and writes each possible situation as a separate test item to verify that the entire AHB (Note: Advanced High Speed ​​Bus System designed by ARM Company) system is fully compliant with the protocol. required. This verification method is inefficient, takes a long time, and it is difficult to detect false correlations between various test items. [0003] At present, the more popular testing methods are based on the verification methodology of random vector generation with constrai...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
CPCG06F11/3668
Inventor 徐迪宇姜勇吉王宗传
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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