SystemVerilog based random verification platform and method

A random verification and platform technology, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve problems such as increasing the complexity of verification platforms, meet the needs of simulation verification, facilitate error checking, and improve versatility. Effect

Inactive Publication Date: 2015-03-04
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Random stimuli can be used to check different functional coverage points and reduce

Method used

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  • SystemVerilog based random verification platform and method

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Embodiment 1

[0017] The random verification platform based on SystemVerilog described in this embodiment, as attached figure 1 As shown, the random verification platform includes a Test module, a Generator module, a Driver module, a DUT module, a Golden Reference module, a Scoreboard module, a Coverage module and an Environment module;

[0018] Among them, the Test module is used to instantiate the environment to start the test; the default values ​​of many options can be set in the Test module, including dcb_arb_priority (simulation corresponds to PRIORITY), dcb_dir_any (simulation corresponds to DIR), flush_dcb_bank (simulation corresponds to FLUSH), Initialization (Simulation corresponds to INI);

[0019] Described Generator module: this module produces all test excitations, and test excitation is delivered to Driver module; Described Driver module: this module receives the test excitation of generator module, and drives to DUT and Golden Reference two modules; Described Scoreboard modu...

Embodiment 2

[0023] In the random verification platform based on SystemVerilog described in this embodiment, on the basis of Embodiment 1, the Generator module also includes two modules, Config and Packet, wherein the Config module: namely Configuration, can randomly generate configuration data according to configuration requirements ; Described Packet module: randomly generate the input of the design to be tested, the value of the address can repeat the previous address, can also be equal to the previous address of the previous address, can also be equal to the next address of the previous address, or can be equal to other random value; the Packet module will also randomly generate the input of the Golden Reference module.

[0024] In this embodiment 2, described Driver module receives the test excitation of generator module, and drives to DUT and Golden Reference two modules; By wait_cycles provided in Packet module, the transmission interval of input excitation can be randomized, and the...

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Abstract

The invention discloses a SystemVerilog based random verification platform and method, and relates to the field of chip design. The SystemVerilog based random verification platform comprises a Test module, a Generator module, a Driver module, a DUT (device under test) module, a Golden Reference module, a Scoreboard module, a Coverage module, an Environment module and the like, wherein the Test module instantiates environment to start testing; the Generator module generates all test excitation; the Driver module receives the test excitation and drives the DUT module and the Golden Reference module, the Scoreboard module judges the function correctness of the DUT module, and the Coverage module accounts the coverage of the test. By means of the random verification method, interfaces among chips are controlled and monitored, the universality of verification environment is improved, and the verification efficiency is substantially improved.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a random verification platform and method based on SystemVerilog. Background technique [0002] Randomized testing can be applied to any type of design, especially if the design has a relatively large test space or a large number of interaction scenarios. It is a very important function to hit some expected function points by adopting random testing, because verification engineers may not be able to list all the function points. Random testing can create unusually concurrent or asynchronous events to test unique, complex behaviors in a design. [0003] In the process of verifying the function points of the test object using randomly generated test stimuli, record the coverage rate of the test object’s function points before and after each test stimuli is run, and save the test stimuli that cause the coverage to change to the preset effective In the incentive information; complex chip...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 丁雪
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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