System and method for testing single-packet regular matching logic

A logic and single-package technology, applied in the field of logic testing, can solve problems such as complex and difficult mapping relationships, and achieve the effect of improving efficiency and improving the efficiency of functional verification

Active Publication Date: 2012-06-13
DAWNING INFORMATION IND BEIJING +1
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  • Abstract
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Problems solved by technology

[0005] However, in the process of testing large-scale logic, since the incentive data and the corresponding data are very large, and the mapping relations...

Method used

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  • System and method for testing single-packet regular matching logic

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Embodiment Construction

[0023] The invention adopts the systemVerilog language to realize the excitation generator, the reference model, the response analyzer, the rule storage device simulation model and the PCIe simulation model (for the interaction between the host computer and the logic under test).

[0024] At present, the logic test methods include generating stimulus generators and corresponding analyzers (TCL language) through scripting language, or building the entire test platform by verilog language. Since systemverilog language is an object-oriented logic test language, it has rich random functions and constraint mechanisms. , can generate a powerful test platform flexibly and conveniently, significantly improve the test efficiency, and ensure that the product is launched without functional defects in a short period of time.

[0025] figure 1 It is a logical schematic diagram of a single-packet regular matching function of the present invention, and the system for testing single-packet re...

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Abstract

The invention provides a method for testing single-packet regular matching logic. A peripheral component interface express (PCIe) simulation model simulates the characteristic of a PCIe bus and receives a host command which comprises a write command and a read command. Compared with the prior art, the method has the advantages that: 1) the efficiency of a program which is compiled by using a SystemVerilog language is quite high, a complicated function can be realized by using smaller code line number, and validation efficiency is improved; and 2) a constraint-based random simulation validation method using the SystemVerilog language is a high-efficiency function validation method, the validation efficiency of the function can be greatly improved, and the functional defect of a product which is sold in the market is avoided.

Description

technical field [0001] The invention belongs to the field of logic testing, and in particular relates to a system and method for testing single-packet regular matching logic. Background technique [0002] The functional requirements of logic can generally be translated into the form of "some kind of stimulus is applied, and the logic should make a certain response". In order to verify whether a certain functional requirement in the logic requirements specification is realized, it is necessary to apply various stimulus data to the logic (such as configuring registers, sending data packets to the logic, etc.), and then judging whether the corresponding data of the logic is consistent with the requirements specification Consistent with the definition in . If the stimulus data applied to the logic is sufficient, and the logic's response to the stimulus is correct, then the logic function is correctly implemented. The passing of the logic test needs to meet two conditions: the ...

Claims

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Application Information

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IPC IPC(8): G06F11/25
Inventor 纪奎白宗元李锋伟张磊邵宗有
Owner DAWNING INFORMATION IND BEIJING
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