58 results about "Peripheral bus" patented technology

The invention relates to an audio SOC chip, an audio subsystem interface module thereof, and electronic equipment, and the audio subsystem interface module comprises a plurality of downlink path units which are used for carrying out the downlink processing of at least one path of digital audio data obtained from an application processor chip and / or a digital signal processing chip through a peripheral bus interface module, the audio data is output through the audio data transmission interface module; the plurality of uplink path units are used for performing uplink processing on at least one path of digital audio data input through the audio data transmission interface module and outputting the processed data to the application processor chip and / or the digital signal processing chip through the peripheral bus interface module; and the plurality of loopback path units are used for converging the at least one path of digital audio data input through the audio data transmission interface module and the digital audio data obtained by performing downlink processing through any downlink path unit in the plurality of downlink path units, and outputting the digital audio data through the audio data transmission interface module, so that the power consumption of a chip is reduced.

A network switch, for use in an Ethernet network in a vehicle, includes multiple ports, a switch unit, a peripheral bus, multiple DMA engines and a mapping engine. The ports connect to the Ethernet network. The switch unit forwards packets s among the ports. The peripheral bus connects to a host that runs host applications. The DMA engines transfer packets from the host applications via the peripheral bus to the switch unit. The mapping engine constructs a mapping that maps between (i) bus functions of the peripheral bus that are assigned to the host applications, and (ii) respective ones of the DMA engines, and configures the switch unit, in accordance with the mapping, to permit forwarding of a packet sent from a host application only upon verifying that a DMA engine that transferred the packet is mapped to the bus function assigned to the host application.

A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.

Systems, devices, and methods related to a deep learning accelerator and memory are described. An integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or connections among the random access memory, the deep learning accelerator and the central processing unit; and an input / output interface to an external peripheral bus. While the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.

The invention relates to an audio subsystem interface module, an audio SOC chip and electronic equipment, and the audio subsystem interface module is characterized in that the audio subsystem interface module is connected between a peripheral bus interface module and peripheral equipment, and the peripheral bus interface module is connected with an application processor chip and a digital signal processing chip; the audio subsystem interface module comprises a plurality of downlink path units, a plurality of loopback path units and an audio data transmission interface module; the plurality of downlink path units and the plurality of loopback path units respectively comprise at least one synchronous first-in first-out data buffer SFIFO; and the plurality of synchronous first-in first-out data buffers are used for realizing back pressure logic of the audio subsystem interface module. The power consumption of the SOC chip can be reduced by introducing the plurality of downlink path units and the plurality of loopback path units, and data overflow can be avoided by performing back pressure on the preceding-stage node based on the plurality of synchronous first-in first-out data buffers in the path units.

The invention relates to tunneling of peripheral bus protocol traffic over a consistent fabric and an inter-chip or inter-die bus. A peripheral device includes: a master chip, the master chip including a coherent interconnect; one or more first peripheral bus modules; an inter-chip (C2C) or inter-die (D2D) interface; and one or more tunnel adapters. A coherency interconnect is used to connect electronic components of a peripheral device according to a coherency interconnect protocol. The one or more first peripheral bus modules are configured to communicate according to a peripheral bus protocol. The C2C or D2D interface is to communicate with an auxiliary chip comprising one or more second peripheral bus modules over a C2C or D2D bus. The one or more tunnel adapters are configured to transmit peripheral bus packets of a peripheral bus protocol between the first and second peripheral bus modules over the coherency interconnect and the C2C or D2D bus by transitioning between the peripheral bus packets, messages of the coherency interconnect protocol, and C2C or D2D bus messages.

This invention discloses a quantum-resistant method and system based on stateless signatures and execution isomorphism, belonging to the field of quantum-resistant cryptography. First, the sender generates an mKEM broadcast payload based on a modulus error rounding algorithm and signs it using a stateless hash signature algorithm. The receiver performs microsecond-level verification of the signature at the network card driver layer; if verification fails, the signature is silently discarded. After successful verification, a dedicated PQC hardware engine decapsulates the signature, implicitly outputting a pseudo-random scrap key if verification fails. The operating system executes an I / O-aware microarchitecture with isomorphic execution, forcing subsequent processes to maintain physical isomorphism in system calls, memory accesses, and peripheral bus activities, regardless of whether the key is real or scrap. This invention eliminates the risk of private key leakage caused by cloud-based state management through stateless signatures and completely eliminates distinguishable side-channel fingerprints across the entire link through physical-level execution isomorphism, achieving system-level quantum-resistant security in high-concurrency scenarios.

A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

A computing system (102), comprises a system memory (116) including a lock array (204), a processor (112) coupled to the system memory (116), a peripheral bus (115) coupled to the system memory (116), and a hardware accelerator (122). The hardware accelerator (102) comprises a bus interface (141) coupled to the peripheral bus (115), a lock circuit (140) coupled to the bus interface (141), and a plurality of kernel circuits (138) coupled to the lock circuit (140) and the bus interface (141). The plurality of kernel circuits (138) provide lock requests to the lock circuit (140), the lock requests for data (202) stored in system memory (116) of the computing system (102). The lock circuit (140) is configured to process the lock requests from the plurality of kernel circuits (138) and to issue atomic transactions over the peripheral bus (115) through the bus interface (141) based on the lock requests. The lock circuit (140) is further configured to issue atomic transactions in competition with competing threads (139) executed by the processor (112) to check the lock array (204) in the system memory (116) for exclusive access to the data (202). The lock array (204) is indexed by identifiers for certain portions of the data (202) stored in the system memory (116). The lock circuit (140) provides a single source of atomic transactions over the bus interface (141) and maintains a kernel lock array (206) indexed by identifiers for the data (202) stored in the system memory (116).

The invention provides an aluminum electrolysis cell cathode bus short circuit device and an implementation method thereof, and relates to the technical field of aluminum electrolysis. Short-circuit ports are preset at the end parts of cell periphery buses of the device and are used for being connected with a short-circuit device when the cells are stopped, and the cell periphery buses between adjacent electrolytic cells are physically isolated through air intervals in a non-short-circuit state; each short circuit port is arranged between two adjacent sections of groove periphery buses, comprises an insulating block, an insulating sleeve and a composite insulating stud, and is used for constructing physical isolation and forming detachable connection when needed; and the short-circuit device is a pluggable conductive structural member, comprises a conductive block and a crimping contact surface, and is used for being inserted into the short-circuit port when the cell needs to be stopped, so that the electrical connection between the peripheral buses of the adjacent electrolytic cells is realized. According to the method, the short circuit port is arranged, the short circuit device is prepared, and the short circuit device is inserted during cell stopping to realize short circuit operation, so that the method has the advantages of simple structure, high safety, high operation efficiency and convenience in maintenance, and is suitable for aluminum electrolysis series devices with the current intensity of 200-800kA.

A photovoltaic cell (1) including a first front collector layer (4), an amorphous silicon layer (6) on the first layer (4) and a second conductive layer (8) on the amorphous silicon layer (6). Electrical connection of the second conductive layer (8) to the first layer (4) is made through the amorphous silicon layer (6) at the periphery of the photovoltaic cell, the electrically conductive layer (8) comprising a positive peripheral bus (8′), which is connected to the TCO first layer (4) and to at least one positive connection terminal at one end of the positive peripheral bus, and a negative peripheral bus, which is connected to a negative connection terminal, and the positive and negative peripheral buses being asymmetrical relative to one another, with the positive peripheral bus being longer than the negative peripheral bus.

The present disclosure relates to an audio subsystem interface module, an audio SOC chip, and an electronic device. The audio subsystem interface module includes: an audio subsystem interface module connected between a peripheral bus interface module and a peripheral device; the peripheral bus interface module is respectively connected to an application processor chip and a digital signal processing chip; the audio subsystem interface module includes multiple downstream path units, multiple loopback path units, and an audio data transmission interface module; the multiple downstream path units and the multiple loopback path units each include at least one synchronous first-in-first-out data buffer (SFIFO); the multiple synchronous first-in-first-out data buffers are used to implement backpressure logic for the audio subsystem interface module. The present disclosure reduces the power consumption of the SOC chip by introducing multiple downstream path units and multiple loopback path units, and avoids data overflow by applying backpressure to the previous node based on the multiple synchronous first-in-first-out data buffers in the path units.

The embodiment of the invention discloses computing equipment, an asset management method and management terminal equipment. The computing device comprises a monitoring circuit, a baseboard management controller (BMC) and a peripheral bus which are connected with the monitoring circuit, a direct memory access (DMA) controller connected with the BMC, and a peripheral controller or a bus controller connected with the peripheral bus, the monitoring circuit is used for monitoring a bus signal of a peripheral bus, if the bus signal meets a preset level change condition, a hardware interrupt signal is sent to the BMC, and the preset level change condition indicates that peripheral change exists; the BMC is used for executing an interrupt service program corresponding to the hardware interrupt signal to trigger the DMA controller to read first hardware information from a preset source address and store the first hardware information to a target storage address, and the first hardware information is used for determining asset information of the computing device; the preset source address is an address, used for storing the first hardware information, of a peripheral controller or a bus controller in the computing equipment under the condition that the peripheral is changed.

A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.

An input / output (I / O) device is coupled to a processor via a first peripheral bus and a second peripheral bus. The I / O device is configured to expose a first physical function (PF) and a second PF to a virtual machine (VM) executing on the processor. A first virtual function (VF) associated with the first PF is assigned to the first peripheral bus, and a second VF associated with the second PF is assigned to the second peripheral bus. The first VF and the second VF are exposed as a single VF to the VM. The VM can perform transactions with the I / O device via the single VF using the first peripheral bus and the second peripheral bus.

The utility model relates to a photovoltaic cell (1). The photovoltaic cell (1) comprises a first front collector layer (4), an amorphous silicon layer (6) on the first layer (4), and a second conductive layer (8) on the amorphous silicon layer (6). An electrical connection from the second electrically conductive layer (8) to the first layer (4) is made through the amorphous silicon layer (6). The electrical connection of the second electrically conductive layer (8) to the first layer (4) is made at the periphery of the photovoltaic cell through the amorphous silicon layer (6), the electrically conductive layer (8) comprising a positive peripheral bus (8 ') connected to the TCO first layer (4) and at least one positive connection terminal at one end of the positive peripheral bus, and a negative peripheral bus connected to a negative connection terminal, the positive peripheral bus (8') being connected to the TCO first layer (4) and at least one negative connection terminal at one end of the positive peripheral bus. And the positive peripheral bus bar and the negative peripheral bus bar are asymmetric with respect to each other, wherein the positive peripheral bus bar is longer than the negative peripheral bus bar.

Disclosed are a method and apparatus for writing data from an Advanced extensible Interface (AXI) bus to an On-chip Peripheral Bus (OPB), a method and apparatus for reading the data from the AXI bus to the OPB, an electronic device and a non-transitory computer readable storage medium. The method for writing the data includes the following steps: receiving AXI write data sent by the AXI bus (S101); storing the AXI write data into an AXI write cache (S102); performing timing conversion from an AXI bus protocol to an OPB protocol on the AXI write data to obtain OPB write data (S103); and exporting the OPB write data from the AXI write cache to the OPB (S104). By applying the method for writing the data, data interaction between the AXI bus and the OPB is completed, the cost is reduced, and the project development efficiency is improved.

A system having: a compute express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocated from more than one of the memory devices.

A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

The invention belongs to the technical field of submarine-launched unmanned aerial vehicle monitoring and control, and particularly relates to a submarine-launched unmanned aerial vehicle launch signal monitoring method. Comprising an MCU module, a signal acquisition module, a serial port expansion module, a communication module and a logic control module, the MCU module comprises an STM32 chip, an AHB system bus, an APB peripheral bus, a BAM data acquisition module and an LQFP minimum hardware module; the signal acquisition module comprises a vibration sensor, an electromagnetic signal sensor and an acoustic vibration signal acquisition chip which are arranged on a submarine-launched unmanned aerial vehicle launch canister, and an accelerometer, an electronic compass and an unmanned aerial vehicle pose signal acquisition chip which are located on an unmanned aerial vehicle; the communication module comprises an LTE communication assembly arranged on the unmanned aerial vehicle; the method and the device are used for monitoring each platform parameter in the launching process of the unmanned aerial vehicle and each parameter attribute in the launching process of the unmanned aerial vehicle so as to realize stable control of the launching process of the unmanned aerial vehicle.

This invention discloses a multi-peripheral bus multiplexing design system and method based on IIC, belonging to the field of integrated circuit communication technology. The system includes: a virtual bus interface module, an instruction cache module, a virtual bus kernel module, an instruction execution module, and a result return module. The method includes: S1 instruction reception and caching; S2 instruction decision-making and scheduling; S3 instruction execution and bus control; S4 result return. This invention achieves multi-device multiplexing through a software virtual bus kernel, eliminating the need for a dedicated hardware multiplexer and avoiding the use of additional IIC addresses; it supports concurrent access by multiple applications and preemption of urgent tasks through priority scheduling and interrupt handling; and it ensures that only one slave device communicates at a time through SDA line on / off control. This invention features low hardware cost, low software complexity, and strong real-time performance, effectively solving the problem of multiplexing IIC peripherals with the same address.

The application discloses a kind of pool management design methods and systems of peripheral resource under multiple SOC, it is related to pool management technical field, comprising: group SOC set, and extract the first SOC in the SOC set, wherein the first SOC has first peripheral equipment;The first peripheral equipment is connected to predetermined peripheral bus by full exchange high-speed bus, wherein the predetermined peripheral bus refers to FPGA program;The bus scanning result is obtained by dynamically scanning the FPGA program;Read predetermined start strategy, and whether the bus scanning result meets predetermined start constraint according to the predetermined start strategy;If the bus scanning result meets the predetermined start constraint, issue start instruction, and drive load is carried out to target drive based on the start instruction.The application solves the technical problem that the existing technology has low peripheral resource sharing efficiency, and achieves the technical effect of efficient management of peripheral resource.

The invention discloses a pooling management design method and system for peripheral resources under multiple SOCs, and relates to the technical field of pooling management, and the method comprises the steps: building an SOC set, and extracting a first SOC in the SOC set, the first SOC being provided with a first peripheral; the first peripheral is connected to a preset peripheral bus through a full-exchange high-speed bus, and the preset peripheral bus refers to an FPGA program; dynamically scanning the FPGA program to obtain a bus scanning result; reading a predetermined starting strategy, and judging whether the bus scanning result conforms to a predetermined starting constraint or not according to the predetermined starting strategy; and if the bus scanning result accords with the preset starting constraint, sending a starting instruction, and carrying out drive loading on a target drive based on the starting instruction. The technical problem of low peripheral resource sharing efficiency in the prior art is solved, and the technical effect of efficient management of peripheral resources is achieved.

The present invention discloses a mixed digital-analog simulation method and system for a decoding module based on the V‑ams language. The simulation method includes the following steps: powering on an analog circuit and performing signal initialization on a decoding circuit of a chip under test; driving an advanced peripheral bus to configure registers; using a data file for stimulation and extracting data; performing data conversion on each channel signal to convert it into two differential signals with a phase difference of 180°; inputting the differential signal into a register transfer stage of an analog circuit for processing; the register transfer stage of the analog circuit processes the data and then outputs it to a register transfer stage of a digital circuit for decoding; collecting and transmitting data to a system control module; performing data comparison and displaying the results. The present invention realizes the joint simulation of digital and analog circuits, ensuring the consistency of the working timing of the analog and digital circuits.

The invention discloses an interface conversion device and a system on chip, and belongs to the technical field of computer communication, and the device comprises an interface control module which is used for carrying out clock domain crossing processing on data at two sides of an advanced peripheral bus interface and an advanced extensible interface; the address generation module is used for remapping a base address of the advanced extensible interface; the state configuration module is used for determining an access address of the advanced peripheral bus interface at the advanced extensible interface according to a preset mapping relation, and configuring and recording a data interaction process on two sides; the bit width conversion module is used for performing bit width conversion on read-write data of the advanced peripheral bus interface and the advanced extensible interface; and the transmission control module is used for transmitting control signals of the advanced peripheral bus interface and the advanced extensible interface and transmitting read-write data of the advanced peripheral bus interface and the advanced extensible interface according to configuration data of the state configuration module. Through the device, protocol conversion from the APB to the AXI can be realized.

The invention discloses a peripheral device with a loose sequence bus interface. Peripheral devices include a bus interface and circuitry. The bus interface is to exchange bus transactions through a peripheral bus that allows disordered transfer of at least a portion of the bus transactions. The circuitry is to generate a plurality of streams of bus transactions, select one or more streams from the plurality of streams that require transaction ordering, enforce transaction ordering in the bus transactions of the selected streams, and send the bus transactions to the peripheral bus over the bus interface.

The invention discloses a method and a device for upgrading firmware of a digital signal processor and electronic equipment. The method comprises the following steps: acquiring a slave state of a slave digital signal processor by a host system-on-chip; selecting an upgrading mode by the host system-on-chip according to the slave state; and carrying out firmware upgrading on the slave digital signal processor by the host system-on-chip through bridging from a serial peripheral interface to an advanced peripheral bus SPI2APB according to the upgrading mode. According to the method, the host SoC and the slave DSP complete firmware upgrading on the basis of SPI2APB bridging, no extra switch chip needs to be configured in the process, and no time division multiplexing needs to be performed on a DSP Flash memory, so that non-inductive and empty chip upgrading is realized, the upgrading cost is reduced, and the upgrading efficiency is improved.

A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

The invention provides a data processing method, which is applied to an embedded system, the embedded system comprises a microprocessor and a peripheral bus, the data processing method comprises the following steps: the microprocessor calls an instruction in an instruction set to process first data, the instruction set is stored in the microprocessor, and the peripheral bus is connected with the microprocessor; the instructions comprise a read access instruction, a write access instruction, a judgment instruction, a waiting instruction, an interrupt instruction, a logical operation instruction and a jump instruction, and the first data comprises data of a peripheral bus and / or data of a sensor. According to the method disclosed by the invention, the microprocessor calls the stored instruction set to process the first data, so that the situation that the central processing unit processes the first data by using a complex instruction set is avoided, and the power consumption of data processing is reduced.

The present disclosure relates to cross-address space bridging. A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and a first system component and a second system component. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to enable the peripheral device to access the second address space associated with the second system component.