14 results about "Peripheral bus" patented technology

This invention discloses a quantum-resistant method and system based on stateless signatures and execution isomorphism, belonging to the field of quantum-resistant cryptography. First, the sender generates an mKEM broadcast payload based on a modulus error rounding algorithm and signs it using a stateless hash signature algorithm. The receiver performs microsecond-level verification of the signature at the network card driver layer; if verification fails, the signature is silently discarded. After successful verification, a dedicated PQC hardware engine decapsulates the signature, implicitly outputting a pseudo-random scrap key if verification fails. The operating system executes an I / O-aware microarchitecture with isomorphic execution, forcing subsequent processes to maintain physical isomorphism in system calls, memory accesses, and peripheral bus activities, regardless of whether the key is real or scrap. This invention eliminates the risk of private key leakage caused by cloud-based state management through stateless signatures and completely eliminates distinguishable side-channel fingerprints across the entire link through physical-level execution isomorphism, achieving system-level quantum-resistant security in high-concurrency scenarios.

The embodiment of the invention discloses computing equipment, an asset management method and management terminal equipment. The computing device comprises a monitoring circuit, a baseboard management controller (BMC) and a peripheral bus which are connected with the monitoring circuit, a direct memory access (DMA) controller connected with the BMC, and a peripheral controller or a bus controller connected with the peripheral bus, the monitoring circuit is used for monitoring a bus signal of a peripheral bus, if the bus signal meets a preset level change condition, a hardware interrupt signal is sent to the BMC, and the preset level change condition indicates that peripheral change exists; the BMC is used for executing an interrupt service program corresponding to the hardware interrupt signal to trigger the DMA controller to read first hardware information from a preset source address and store the first hardware information to a target storage address, and the first hardware information is used for determining asset information of the computing device; the preset source address is an address, used for storing the first hardware information, of a peripheral controller or a bus controller in the computing equipment under the condition that the peripheral is changed.

A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.

A system having: a compute express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the compute express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocated from more than one of the memory devices.

This invention discloses a multi-peripheral bus multiplexing design system and method based on IIC, belonging to the field of integrated circuit communication technology. The system includes: a virtual bus interface module, an instruction cache module, a virtual bus kernel module, an instruction execution module, and a result return module. The method includes: S1 instruction reception and caching; S2 instruction decision-making and scheduling; S3 instruction execution and bus control; S4 result return. This invention achieves multi-device multiplexing through a software virtual bus kernel, eliminating the need for a dedicated hardware multiplexer and avoiding the use of additional IIC addresses; it supports concurrent access by multiple applications and preemption of urgent tasks through priority scheduling and interrupt handling; and it ensures that only one slave device communicates at a time through SDA line on / off control. This invention features low hardware cost, low software complexity, and strong real-time performance, effectively solving the problem of multiplexing IIC peripherals with the same address.

The invention discloses a method and a device for upgrading firmware of a digital signal processor and electronic equipment. The method comprises the following steps: acquiring a slave state of a slave digital signal processor by a host system-on-chip; selecting an upgrading mode by the host system-on-chip according to the slave state; and carrying out firmware upgrading on the slave digital signal processor by the host system-on-chip through bridging from a serial peripheral interface to an advanced peripheral bus SPI2APB according to the upgrading mode. According to the method, the host SoC and the slave DSP complete firmware upgrading on the basis of SPI2APB bridging, no extra switch chip needs to be configured in the process, and no time division multiplexing needs to be performed on a DSP Flash memory, so that non-inductive and empty chip upgrading is realized, the upgrading cost is reduced, and the upgrading efficiency is improved.

A system having: a computer express link fabric; a plurality of memory devices having random access memory cells, a memory bus; a main memory; at least one processing device connected to the main memory via the memory bus, and connected to the computer express link fabric; a peripheral bus; and a plurality of memory sub-systems connected to the at least one processing device via the peripheral bus. A plurality of portions of the random access memory cells in the plurality of memory devices are allocated respectively as a plurality of host memory buffers for the plurality of memory sub-systems. Each memory buffer can have random access memory cells allocate from more than one of the memory devices.

A Single Event Upset Protector (SEUP) solution receives assembly code corresponding to a program and generates a primary thread and a shadow thread, each operating in different address spaces of an unhardened processor. The SEUP solution inserts swizzling operations in the shadow thread to maintain canonical pointer values and inserts turnouts in both threads to look for checkpoints. A SEUP solution insert a SEUP (e.g., hardware) between the unhardened processor and (a) a data memory and (b) a peripheral bus. The SEUP caches memory writes to the data memory and I / O writes to the peripheral bus. The SEUP restarts the primary thread and the shadow thread at a previous checkpoint when a watchdog indicates a hang and when the cached memory writes and the cached I / O writes by the primary thread to not match the cached memory writes and the cached I / O writes by the shadow thread.

Described are techniques for video bridging for conversion of IP network video streams to the USB Video Class (UVC). The conversion of IP video to UVC video can include the use of software-only conversions and hardware assisted conversions, and can be done within purpose-built “conversion” devices or as software only solutions operating within applications or drivers within the operating systems of the “end nodes”. The end-nodes simultaneously see and use multiple USB UVC video sources. The conversion process can also convert the USB UVC video control protocol to IP Video Stream control protocols.

The technology is generally directed to multi-channel memory in a system on chip (SoC) device. Multiple memory channels are associated with a single common microcontroller instead of including a microcontroller with each channel. The common microcontroller is located centrally on the chip along with the memory subsystem. The single microcontroller receives commands from a plurality of host processing entities (PEs) including one or more of a central processing unit, a debugging architecture, and a power manager The processor receives commands from the host PEs from a software sequencer of the compute device, while the single microcontroller communicates with each of the plurality of memory channels through an advanced peripheral bus. The single microcontroller aggregates requests from the host PEs and manages the programming of the memory controller, the PHY, and the dynamic random access memory for the plurality of memory channels.

An electrolytic cell body is internally divided into a left electrolytic cell and a right electrolytic cell, one side of the left electrolytic cell is provided with a plurality of forward electricity-feeding upright post buses, and one side of the right electrolytic cell is provided with a plurality of reverse electricity-feeding upright post buses. The forward power-in stand column bus and the reverse power-in stand column bus are arranged on the two sides of the electrolytic cell body respectively, the forward power-in stand column bus is connected with an anode large bus A in the left electrolytic cell, and the reverse power-in stand column bus is connected with an anode large bus B in the right electrolytic cell. Wherein the cell periphery bus of the left electrolytic cell is connected with the forward electricity-feeding upright post buses of the other electrolytic cells, and the cell periphery bus of the right electrolytic cell is connected with the reverse electricity-feeding upright post buses of the other electrolytic cells. According to the utility model, when the two sides of the electrolytic bath are electrified at the same time, a bus system can operate stably and safely, and the aim of reducing the series voltage is fulfilled at the same time.

The invention provides a debugging system and a debugging method for an end-side processor. The debugging system comprises a JTAG (Joint Test Action Group) interface, an input / output function selector, a DTM (Debugging Transmission Module), an APB (Advanced Peripheral Bus) and a plurality of cores in the end-side processor. An input and output function selector on a JTAG interface side is designed, three different JTAG links are selected according to JTAG link selection SEL signal values, two of the JTAG links can be directly connected with a core in an end-side processor, the other JTAG link is connected with an advanced peripheral bus APB through conversion of a debugging transmission module DTM and then connected with the core in the end-side processor, and the JTAG links can be directly connected with the core in the end-side processor. Debugging independence is enhanced, multiple cores can be debugged according to different addresses, expansibility is high, and universality is high. And meanwhile, a double-line JTAG interface which can coexist with a five-line JTAG is defined in the DTM, so that external pin resources are saved, and a communication mode is simplified.

A photovoltaic cell (1) including a first front collector layer (4), an amorphous silicon layer (6) on the first layer (4) and a second conductive layer (8) on the amorphous silicon layer (6). Electrical connection of the second conductive layer (8) to the first layer (4) is made through the amorphous silicon layer (6) at the periphery of the photovoltaic cell, the electrically conductive layer (8) comprising a positive peripheral bus (8′), which is connected to the TCO first layer (4) and to at least one positive connection terminal at one end of the positive peripheral bus, and a negative peripheral bus, which is connected to a negative connection terminal, and the positive and negative peripheral buses being asymmetrical relative to one another, with the positive peripheral bus being longer than the negative peripheral bus.

The invention discloses a system-on-chip, a data processing method and a related device, the system-on-chip comprises a central processing module and a security processor module, the central processing module comprises a central processing unit, an advanced extensible interface, a switching bridge and a first advanced peripheral bus, the central processing unit is connected with the advanced extensible interface, and the switching bridge is connected with the first advanced peripheral bus. The advanced extensible interface is connected with the first advanced peripheral bus through the switching bridge, the safety processing module comprises a safety processor, and the safety processor is connected with the advanced extensible interface and the first advanced peripheral bus. The security processor is added in the system-on-chip, so that the central processing unit can process other non-security tasks while the security processor processes the security tasks, the security task processing efficiency of the operating system is improved, the load of the central processing unit is reduced, and the initialization time of the operating system is shortened.