System-on-a-Chip structure having a multiple channel bus bridge

Abstract

A system-on-a-chip integrated circuit structure includes a bridge having a plurality of channels, a processor local bus connected to the bridge (wherein the bridge includes a first channel dedicated to the processor local bus), at least one logic device connected to the processor local bus, a peripheral device bus connected to the bridge (wherein the bridge includes a second channel dedicated to the peripheral device bus), at least one peripheral device connected to the peripheral device bus, at least one memory unit connected to the bridge (wherein the bridge includes a third channel dedicated to the memory unit), and at least one input / output unit connected to the bridge (wherein the bridge includes a fourth channel dedicated to the input / output unit).

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to System-on-a-Chip architecture and more particularly to an improved bridge that provides multiple virtual channels for the devices connecting to the bridge to reduce latencies.[0003]2. Description of the Related Art[0004]Conventional component-based System-on-a-Chip (SoC) communication architectures achieve poor performance. This is primarily due to the blocking nature of their on-chip communication structures associated with handshake protocols, interconnecting processors and their peripheral Intellectual Property (IP) blocks, which induces latencies that degrade performances of bus system hierarchies. Existing chipset bridges connect processors running at clock speeds of 500 MHz or more to system memories and to I / O's that operate at much lower speed, typically below 100 MHz. Conventionally, the main memory subsystems (fast DRAM) offer high throughput, but they often require s...

AI Technical Summary

Problems solved by technology

Conventional component-based System-on-a-Chip (SoC) communication architectures achieve poor performance.

This is primarily due to the blocking nature of their on-chip communication structures associated with handshake protocols, interconnecting processors and their peripheral Intellectual Property (IP) blocks, which induces latencies that degrade performances of bus system hierarchies.

Conventionally, the main memory subsystems (fast DRAM) offer high throughput, but they often require several system clock cycles of latency.

Increasing the frequency is very hard, and strictly relying on it is not a practical solution.

Improvements to the CPU's processing power result in requirements for more bandwidth, and real time applications impose low latencies.

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