9 results about "Networking hardware" patented technology

A black screen control system for nitric acid production, comprising network hardware nodes deployed in a local area network and control units running on the network hardware nodes, the control units are independently deployed at each operation station and adopt a multi-thread isolation architecture. The invention allocates time-consuming bottom layer data collection, processing and front-end UI interaction to independent threads for asynchronous execution, ensuring the ultimate smoothness and stability of the system under high concurrency; the state control and abnormal response are separated, the system enters the energy-saving black screen state under normal conditions to reduce power consumption, and when an abnormal signal occurs, the system is instantly awakened across threads and a safety alarm is triggered, realizing true safe unattended operation; the control units are independently deployed and run at each operation station, and are uniformly scheduled by a master control module, avoiding the whole line paralysis caused by single point failure or network fluctuation, and ensuring the absolute independence and reliability of a single device.

The application discloses a 2-group signed tensor calculation circuit structure based on a 6-bit approximate full adder, relates to the field of neural network hardware acceleration, and comprises a 6-bit approximate full adder module, a signed 8*8 approximate multiplier circuit structure based on the 6-bit approximate full adder and the 2-group signed tensor calculation circuit structure based on the 6-bit approximate full adder. Since the neural network accelerator can sacrifice part of the accuracy of data in exchange for the optimization of delay, area and power consumption of a circuit structure, the 6-bit approximate full adder module ignores part of the carry, thereby reducing the circuit area and lowering the circuit power consumption, the signed 8*8 multiplier calculation process and the 2-group signed tensor calculation process are optimized by using the 6-bit approximate full adder module, approximate calculation is introduced at some positions, and in exchange for the improvement of area and power consumption of the circuit structure, part of the accuracy is lost.

This invention relates to the field of network hardware security technology, specifically disclosing a device authentication and key derivation method and electronic device based on FPGA physical binding. The method includes: in response to device power-on, blocking the protected data path; calling the underlying hardware primitives of the FPGA to read the chip's unique physical identifier sequence; comparing the unique physical identifier sequence with preset authentication information to generate an authentication result; and generating a working key based on the unique physical identifier sequence and an external input key when authentication is successful. This invention restricts the protected data path at the initial power-on stage of the device and combines the chip-bound physical identifier sequence with the external input key to dynamically generate the working key, reducing reliance on static key storage mechanisms and mitigating the risk of configuration data being copied to unauthorized chips and continuing to operate.

The application provides a dynamic adjustment method, a management device and a system of a vehicle network. The dynamic adjustment method comprises: acquiring data transmission requests of each first function module and each second function module respectively; acquiring network state data of a vehicle-mounted network and external networks corresponding to each first function module respectively; determining network working modes of each first function module according to the network state data and the data transmission requests; determining network use permissions of each first function module and each second function module according to function attributes of each first function module and each second function module; and controlling each first function module to work in a corresponding network working mode, and controlling each first function module and each second function module to transmit data based on the vehicle-mounted network and / or each external network according to the corresponding network use permissions. According to the application, the defects of network hardware can be solved through software, and the real-time performance of the function of the vehicle network is improved.

The application provides in-memory index-based multilayer perceptron high-energy-efficiency in-memory calculation, and relates to the technical field of neural network hardware acceleration. The method comprises the following steps: extracting weight parameters of each layer in a multilayer perceptron model, generating a lookup table, and storing the lookup table in on-chip memory; according to the network layer type, dynamically loading a weight sub-table from the lookup table into a multiple address concurrent cache to form a local lookup table for single-cycle multi-address parallel access; according to the network layer type and a block strategy, batch reading of input feature vectors is performed and the input feature vectors are divided into multiple data blocks; using an activation function, feature values in each data block are transformed into index addresses, the local lookup table is accessed in parallel, and multiple weight data are obtained as lookup table results in a single cycle; through a hierarchical reduction circuit, the lookup table results are accumulated and fused to generate an activation output value; the activation output value is format-converted and written back to a feature data storage as input features of the next layer network or a model inference result. In this way, the requirements of low power consumption and high throughput are effectively balanced.

Disclosed in the present application are a method and apparatus for controlling an Ethernet IP accelerator, and a device and a medium. The method comprises: in response to a sleep or wakeup operation on an operating system, writing, by means of a preset user-mode process, flag information into a file node corresponding to an Ethernet IP accelerator, wherein the flag information comprises a first preset value and a second preset value, the first preset value represents that the operating system is asleep, and the Ethernet IP accelerator needs to be disabled, and the second preset value represents that the operating system is woken up, and the Ethernet IP accelerator needs to be enabled; and by means of a kernel-mode IP accelerator driver, enabling or disabling the Ethernet IP accelerator on the basis of the flag information.

A dedicated extension and emulation proxy for wirelessly extending and emulating several USB-based data stream protocols, such as UVC, UAC, and HID, and standards for connecting high-definition video devices, such as HDMI, in a proxy fashion. The dedicated hardware and software extend these multimedia interfaces over a wireless network link through an emulation wrapper or proxy. The host computer does not virtually see the existence of the wireless connection because its network hardware and software are bypassed to compartmentalize point-to-point networking away from the host computer. The multimedia interface of the host computer is extended wirelessly using surrogate stacks along with protocol emulation transcoding.

This application provides a data packet detection method, apparatus, device, storage medium, and program. The method includes: acquiring multiple network data packets in network hardware and storing them in a virtual address space; the graphics processor includes multiple computing units; acquiring the load status of each computing unit; based on the load status of each computing unit, performing parallel processing on the multiple network data packets through the multiple computing units to obtain the target processing result corresponding to each network data packet; for any given network data packet, if the target processing result corresponding to the network data packet is abnormal, generating detection alarm information for the target processing result of the network data packet, the detection alarm information being used to indicate a security event notification. The method of this application can improve the processing efficiency of data packet detection.

This invention relates to the field of intelligent transportation and vehicle-to-everything (V2X) data processing technology, and discloses a method and system for evaluating the layout of V2X meteorological observation based on data assimilation. The key technical points are: a data cleaning module acquires multi-source hardware sensing data and performs physical interference stripping based on a nonlinear compensation model; a spatial mapping module constructs spatial Gaussian attenuation weights and performs coordinate mapping from discrete point trajectories to a static topological grid; a simulation error module schedules the hardware accelerator to run the simulation environment and deduces the dynamic observation error covariance based on an LSTM network; an assimilation evaluation module first applies the consistent Kalman filtering mechanism to perform physical state assimilation of the meteorological background field and sensor data, then quantifies the information gain scalar of the virtual deployment nodes, and finally configures a multi-objective constraint cost function to solve for the optimal sensor network hardware topology scheme; and an instruction execution module extracts local meteorological slices coupled with traffic flow features, generates physical prevention and control early warning instructions, and issues them for execution.