Function tree structure of micro-processor function validation test case and its automatic generation method

Abstract

The invention provides a function tree structure of a microprocessor function validate testing example and an automatic generating method. A method using the function tree structure describes a testing example, the function tree structure has clear structure layer, relationship between various indication and parameter is clear for processing description using programming language; the function tree structure is mapped to a testing example described by SystemVerilog language using Perl language automatically, only needing inputting corresponding indication according with the function tree structure can generate the testing example automatically, according, time for covering the function tree structure into the testing example is reduced and a validity efficiency is increased, and a product without defect come into a market can be realized in a short time; in addition, the method can increase or decrease indication or parameter according with various product based on existing function tree structure that can be suitable for generating the testing example of various product automatically, according, increase reusability of the testing example.

Description

technical field [0001] The invention relates to a function tree structure and an automatic generation method of a microprocessor function verification test case, in particular to a function tree structure and an automatic generation method of a pipeline microprocessor function verification test case. Background technique [0002] With the development of CAD (computer-aided design) tools and microelectronics manufacturing processes, and the instruction set of microprocessors becomes more and more complex, the design scale becomes larger and larger, and the result of predicting instruction flow becomes more and more important. Unrealistic. Under the pressure of time-to-market, it is difficult for artificially generated instruction sequences to completely cover all possible situations. Due to low verification efficiency, late time-to-market, or functional defects caused by low verification coverage, the losses are all Huge, so traditional directional verification platforms, met...

AI Technical Summary

Problems solved by technology

However, if the SystemVeriiog language is directly used to describe the specific microprocessor function, the reusability of the test case is relatively poor.

To verify the same functions of other microprocessors, it is necessary to make relatively large changes to the original test case description, resulting in relatively low efficiency and prolonging the development cycle of new products

Images