74 results about "Program validation" patented technology

Embodiments of the present application provide a verification system, method, device, medium and program, the verification system comprising: a test excitation generation module for generating a test excitation, the test excitation at least comprising serial data with clock jitter; the CDR circuit model is used for carrying out recovery processing on the input serial data and outputting a recovery result to a next-stage circuit model; the CDR jitter compensation device is used for detecting clock jitter deviation between input and output of the CDR circuit model; determining a control parameter according to the clock jitter deviation; the control parameters are fed back to the test excitation generation module; wherein the control parameter is used for adjusting the clock jitter size of the serial data generated by the test excitation generation module, so as to correct the clock jitter introduced by the CDR circuit model during the recovery processing of the serial data. According to the verification system provided by the embodiment of the invention, the clock jitter can be corrected.

The embodiment of the invention provides a chip verification method, device, system and equipment, a medium and a program.The verification method comprises the steps that a chip is simulated, the chip comprises a program running module and a memory storage module, the program running module is used for running a software program, and a program file of the software program is stored in the memory storage module; executing the simulation case to enable the program running module to call the program file for processing; in the process that the program running module calls the program file, a read-write event of a memory storage module is monitored so as to track the variable change condition of the software program, and the memory storage module is provided with a memory area distributed for variables of the software program; the variable change condition is synchronized and displayed to reflect the running state of the software program, and the running state is used for judging whether the processing of the program running module on the software program reaches the design expectation or not. According to the verification method provided by the embodiment of the invention, software and hardware joint simulation verification of the chip is realized.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

A method may include: a broadcaster computer program generating, for participants in a network in a transaction, a commit, an audit token, and a proof of consistency; the broadcaster computer program broadcasting, the commits, the audit tokens, and the proofs of consistency for each participant to all participants in the network; the participant computer programs generating complimentary commits, complimentary audit tokens, complementary proofs of consistency, proofs of equivalency, and a proof of assets; the broadcaster computer program receiving from each of the participant computer programs, the proof of assets, the complimentary commit, the complimentary audit token, the complementary proof of consistency, and the proof of equivalency; the broadcaster computer program and / or the participant computer programs verifying, the proofs of assets, the proofs of balance, the proofs of consistency, and the proofs of equivalency; and the broadcaster computer program approving the transaction based on the verification.

The invention discloses a robot program verification and real-time data twinning method, relates to the field of robot technology and digital twinning technology, and aims to optimize task design and path planning of a robot in actual work. The method specifically comprises the steps that a script is written by utilizing basic programming languages such as C #, Python and Java, and offline programming software is developed for the robot according to a data interface matched with the corresponding robot; after a working program is written for the robot by using off-line programming software, deploying three-dimensional models of the robot and the production field environment into an unreal engine to form a visual three-dimensional scene, and adding colliders and physical attributes for all the models; robot posture data pre-generated by offline programming software are accessed to a three-dimensional scene, occurrence conditions of accidental collision, joint overrun and singular poses are detected, and after correctness of an offline program is verified, robot data are accessed to an entity robot and the visual three-dimensional scene at the same time. And real-time monitoring and data linkage collaborative display of real-time physical robot operation are realized.

Processing logic in a memory sub-system receives a request to execute a programming operation to program cells of a memory device to a set of programming levels. The processing logic executes a first program verify loop associated with a programming level of the set of programming levels, where the first program verify loop comprises applying an initial bitline voltage to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage. The processing logic executes a subsequent program verify loop associated with the programming level, wherein the subsequent program verify loop comprises applying an adjusted bitline voltage to the subset of the cells.

A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

The present invention discloses a website interaction verification method, device, electronic device and storage medium. When performing website interaction verification, the present invention first sends a verification mini-program code to the user to obtain mini-program parameters, and then, after the mini-program verification parameters are verified to be passed, the website verification code is sent to the user. In this way, the present invention is equivalent to having two verification steps, and its security in use has been greatly improved compared with the traditional single SMS verification; at the same time, during the verification process, the verification mini-program code is introduced as a way to obtain verification parameters, which realizes the concealment processing of the parameters. Compared with the traditional SMS plaintext acquisition method, it is not easily cracked, and the security in use has been further improved; in addition, the present invention uses the mini-program to realize parameter acquisition and verification. Compared with the SMS verification method, it not only does not require fees, reduces costs, but also is not prone to the problem of not being able to receive the verification code.

The invention provides a program verification case construction method and device, a storage medium and equipment. The method comprises the following steps: acquiring a program code of a program to be verified; wherein the program code comprises a plurality of program units; according to the input value and the return value of each program unit, determining a calling relationship between the program units, and generating a program calling sequence according to the calling relationship, the program calling sequence comprising at least two program units having the calling relationship in the program codes; inputting the program calling sequence into a preset use case generation model, and generating a reconstruction code based on the code reconstruction prompt information by using the use case generation model; and inputting the reconstruction code into a use case generation model, and generating a verification use case for the to-be-verified program by using the use case generation model based on the use case generation prompt information. According to the scheme, the coverage rate of the verification case on the function statements in the to-be-verified program is increased, and the reliability of the verification case is improved.

The present application relates to a method for verifying the trust level of a system program based on an edge Internet of Things proxy device, including the following specific steps: Considering the characteristic that the one-time programmable memory eFuse can only be programmed once, the hash value of the secure root key SRK based on the eFuse characteristic is burned in and used as the root of trust; Starting from the boot of the operating system, multi-level verification is carried out until the trust level verification program for boot-up is completed to ensure the security of the boot of the operating system. Based on the premise of being granted credit by the "trust level verification program", the present application verifies the trust levels of the system's built-in application programs and newly added application programs later, eliminating the risk that the traditional "whitelist" protection mechanism loses its protection effectiveness due to the uncontrollability of the secure boot of the operating system, and fundamentally solving the trust problem of the programs running within the system.

Technology for hybrid block management for dynamic SLC verify. The memory system tracks multi-level cell (MLC) programming speed of candidate pages in a three-dimensional NAND memory structure. The memory system determines whether each respective candidate page is eligible for single-level cell (SLC) programming without program verify based on the MLC programming speed. The memory system then programs the candidate pages based on the determination. The memory system may maintain a bitmap that specifies whether a particular candidate page is to receive program verify or not for SLC programming. In one aspect, the MLC programming speed is tracked by noting the number of program pulses used to complete MLC programming.

The present application relates to managing programming convergence associated with memory cells of a memory sub-system. A first program pulse is caused to be applied to a word line associated with a memory cell of a memory sub-system. In response to the first program pulse, a program verify operation is caused to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sense node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sense node is identified. A bit line voltage matching the measured threshold voltage is caused to be applied to a bit line associated with the memory cell.

To efficiently test programs containing loop parts.SOLUTION: A program verification support system 1 stores a first program 100 having a loop part that repeats predetermined processing, as well as initial values of variables in the first program 100 and variable values after execution of the first program 100, by inputting the initial values of the variables into the first program 100, identifies changed portions in the variable values immediately after completing execution of the loop part from the variable values immediately before execution of the loop part begins, generates stub data for the identified changed portions in the variable values, replaces a loop part in a second program 200 corresponding to the first program 100 with the changed portions indicated by the stub data, then executes the second program 200, and outputs data indicating comparison results between execution results of the second program 200 and the variable values after completing execution of the first program 100.SELECTED DRAWING: Figure 1

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a command to perform a program operation on a block of the memory device; determining whether the block is on an exclusion list; determining, in response to determining that the block is not on the exclusion list, whether a value of a media endurance metric of the block satisfies a media endurance metric criterion; performing, in response to determining that the value of the media endurance metric of the block satisfies the media endurance metric criterion, the program operation on the block; determining whether a media health metric of the block satisfies a health threshold criterion; and adding, in response to determining that the media health metric of the block satisfies the health threshold criterion, the block to the exclusion list.

The invention belongs to the field of software model detection, and relates to an interrupt driver sequencing method based on staggered path splitting. Comprising the following steps: inputting a to-be-detected interrupt driver; selecting configuration parameters, and performing function inline preprocessing on the interrupt drive program according to the configuration parameters to obtain a bounded program without function call; staggered path splitting is realized by generating scheduling sequence configuration and code partition configuration, and part of configuration without atomic violation in a scheduling sequence and a code partition is deleted through an optimization process; inserting control codes in the original program according to different scheduling sequences and code partition combinations to generate a plurality of independent sequenced subprograms; executing parallel verification on the plurality of sequenced subprograms according to the number of processor cores in the configuration parameters; and outputting a verification result. According to the method, the large-scale program verification performance can be remarkably improved.

To provide a programming learning program. To create a programming learning program that allows users to easily and simply program using a commercially available personal computer without setting up a special programming environment, and to check the execution status of the computer programs they create. [Solution] A program used to verify the operation of a program created by the users themselves, characterized in that it contains an area for describing the created program.

A memory device includes a memory array having a plurality of memory cells. Control logic operatively is coupled with the memory array. The control logic receives a suspend command while programming multiple data states to a set of the plurality of memory cells of the memory array. The control logic determines whether a trim value associated with a program suspend operation is less than a total number of program verify operations to be performed during a present program verify loop of a programming operation. The control logic, in response to the trim value being less than the total number of program verify operations, causing only a subset of the total number of program verify operations that correspond to the trim value to be performed before causing a program suspend operation to be performed on the set of plurality of memory cells.

This application provides a chip verification method, apparatus, system, device, medium, and program. The verification method includes: simulating a chip, the chip including a program execution module and a memory storage module, the program execution module running a software program, and the program file of the software program being stored in the memory storage module; executing simulation test cases to cause the program execution module to call the program file for processing; monitoring read and write events of the memory storage module during the process of the program execution module calling the program file to track changes in variables of the software program, wherein the memory storage module has a memory area allocated for the variables of the software program; synchronizing and displaying the changes in the variables to reflect the running state of the software program, the running state being used to determine whether the processing of the software program by the program execution module meets the design expectations. The verification method provided by this application implements hardware and software co-simulation verification of the chip.

To efficiently verify a plurality of programs.SOLUTION: An in-vehicle device includes: a storage unit which stores a first program and a second program which is to be executed using the first program; and a verification unit which verifies the first and second programs stored in the storage unit. The in-vehicle device includes a start control unit configured to start the first and second programs when the verification of the first program and the verification of the second program are successful, or configured to start the first program but not to start the second program when the verification of the first program is successful and the verification of the second program fails.SELECTED DRAWING: Figure 3

A method may include: a broadcaster computer program generating, for participants in a network in a transaction, a commit, an audit token, and a proof of consistency; the broadcaster computer program broadcasting, the commits, the audit tokens, and the proofs of consistency for each participant to all participants in the network; the participant computer programs generating complimentary commits, complimentary audit tokens, complementary proofs of consistency, proofs of equivalency, and a proof of assets; the broadcaster computer program receiving from each of the participant computer programs, the proof of assets, the complimentary commit, the complimentary audit token, the complementary proof of consistency, and the proof of equivalency; the broadcaster computer program and / or the participant computer programs verifying, the proofs of assets, the proofs of balance, the proofs of consistency, and the proofs of equivalency; and the broadcaster computer program approving the transaction based on the verification.

A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.

A processing device configures a memory device such that program verify operations are performed for each die of the memory device on different sub-blocks. In configuring the memory device, the processing device configures a first die for performance of program verify operations on a first sub-block within the first die and configures a second die for performance of program verify operations on a second sub-block within the second die. The processing device initiates a programming sequence to write data to the memory device based on the configuring of the memory device. The programming sequence comprises performance of a first program verify operation on the first sub-block within the first die prior to performance of a second program verify operation on the second sub-block within the second die.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

Technology for hybrid block management for dynamic SLC verify. The memory system tracks multi-level cell (MLC) programming speed of candidate pages in a three-dimensional NAND memory structure. The memory system determines whether each respective candidate page is eligible for single-level cell (SLC) programming without program verify based on the MLC programming speed. The memory system then programs the candidate pages based on the determination. The memory system may maintain a bitmap that specifies whether a particular candidate page is to receive program verify or not for SLC programming. In one aspect, the MLC programming speed is tracked by noting the number of program pulses used to complete MLC programming.

The invention aims to provide a multifunctional test module for program verification. The system comprises an MCU unit, the MCU unit is connected with a digital-to-analog converter, a digital multimeter, a pulse signal output and frequency reading unit, a main control chip and flash memory unit, and a pulse width modulation and time division multiplexing unit, the digital-to-analog converter outputs voltage, the voltage is amplified by an operational amplifier circuit and switched by an MUX switch, and the output voltage is converted into the output voltage. The analog-to-digital converter connected to the MCU unit is used for voltage reading, so that control program verification of the digital-to-analog converter and the analog-to-digital converter is realized; the digital multimeter is used for verifying various module programs; the pulse signal output and frequency reading unit outputs PWM signals through the MCU unit, the PWM signals pass through an operational amplifier follower circuit and a comparator, the output signals are connected to the MCU unit to be tested, and the PWM and FREQ program verification function is achieved. The invention is applied to the technical field of electronic test equipment.

The application relates to an authorization method and a storage medium for dynamically generating a License verification mode, which comprises the following steps: obtaining a feature code on a machine, and obtaining a License file through encryption; when a Java application is started, License information in the License file is read, key information in the read information is taken as a member variable name, and value information is taken as a member variable value and is stored in a class dynamically generated by bytecode; an authorization verification class for verifying the License information is generated through bytecode technology; the generated authorization verification class is instantiated, is transmitted into a Java application to generate a verification task, the information in the License file is verified, and if authorization fails, the current program is terminated. The code for verifying the License file is generated through bytecode, so even if a class file of the Java project is obtained, the code for verifying the License cannot be searched through the whole text by decompiling the class file.

A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. An offset value that is based on a loss level associated with the target wordline is selected. During a program verify operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline adjacent to the target wordline or a second wordline adjacent to the target wordline, where the pass through voltage level is a pass through read voltage level reduced by the offset value.

In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.

The application discloses a loop program termination judgment method based on a lexicographic neural rank function and belongs to the field of computer program verification. The method is aimed at a parallel assignment loop program and realizes automatic judgment on the termination of the loop program through the following steps of path extraction and condition construction, adaptive sampling, state transition dataset generation, neural rank function network construction and training of a variable lexicographic dimension, and counterexample guided verification. In the sampling stage, the application adopts an adaptive sampling strategy to avoid parameter sensitivity problems. In the network structure aspect, the application introduces a variable lexicographic dimension feedforward neural network to enhance the expression capacity of the rank function. In the verification stage, the application combines counterexample guidance and a multi-round training mechanism to improve the synthesis efficiency and success rate.