56 results about "Program validation" patented technology

Embodiments of the present application provide a verification system, method, device, medium and program, the verification system comprising: a test excitation generation module for generating a test excitation, the test excitation at least comprising serial data with clock jitter; the CDR circuit model is used for carrying out recovery processing on the input serial data and outputting a recovery result to a next-stage circuit model; the CDR jitter compensation device is used for detecting clock jitter deviation between input and output of the CDR circuit model; determining a control parameter according to the clock jitter deviation; the control parameters are fed back to the test excitation generation module; wherein the control parameter is used for adjusting the clock jitter size of the serial data generated by the test excitation generation module, so as to correct the clock jitter introduced by the CDR circuit model during the recovery processing of the serial data. According to the verification system provided by the embodiment of the invention, the clock jitter can be corrected.

The embodiment of the invention provides a chip verification method, device, system and equipment, a medium and a program.The verification method comprises the steps that a chip is simulated, the chip comprises a program running module and a memory storage module, the program running module is used for running a software program, and a program file of the software program is stored in the memory storage module; executing the simulation case to enable the program running module to call the program file for processing; in the process that the program running module calls the program file, a read-write event of a memory storage module is monitored so as to track the variable change condition of the software program, and the memory storage module is provided with a memory area distributed for variables of the software program; the variable change condition is synchronized and displayed to reflect the running state of the software program, and the running state is used for judging whether the processing of the program running module on the software program reaches the design expectation or not. According to the verification method provided by the embodiment of the invention, software and hardware joint simulation verification of the chip is realized.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

The invention discloses a robot program verification and real-time data twinning method, relates to the field of robot technology and digital twinning technology, and aims to optimize task design and path planning of a robot in actual work. The method specifically comprises the steps that a script is written by utilizing basic programming languages such as C #, Python and Java, and offline programming software is developed for the robot according to a data interface matched with the corresponding robot; after a working program is written for the robot by using off-line programming software, deploying three-dimensional models of the robot and the production field environment into an unreal engine to form a visual three-dimensional scene, and adding colliders and physical attributes for all the models; robot posture data pre-generated by offline programming software are accessed to a three-dimensional scene, occurrence conditions of accidental collision, joint overrun and singular poses are detected, and after correctness of an offline program is verified, robot data are accessed to an entity robot and the visual three-dimensional scene at the same time. And real-time monitoring and data linkage collaborative display of real-time physical robot operation are realized.

Technology for hybrid block management for dynamic SLC verify. The memory system tracks multi-level cell (MLC) programming speed of candidate pages in a three-dimensional NAND memory structure. The memory system determines whether each respective candidate page is eligible for single-level cell (SLC) programming without program verify based on the MLC programming speed. The memory system then programs the candidate pages based on the determination. The memory system may maintain a bitmap that specifies whether a particular candidate page is to receive program verify or not for SLC programming. In one aspect, the MLC programming speed is tracked by noting the number of program pulses used to complete MLC programming.

The present application relates to managing programming convergence associated with memory cells of a memory sub-system. A first program pulse is caused to be applied to a word line associated with a memory cell of a memory sub-system. In response to the first program pulse, a program verify operation is caused to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sense node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sense node is identified. A bit line voltage matching the measured threshold voltage is caused to be applied to a bit line associated with the memory cell.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a command to perform a program operation on a block of the memory device; determining whether the block is on an exclusion list; determining, in response to determining that the block is not on the exclusion list, whether a value of a media endurance metric of the block satisfies a media endurance metric criterion; performing, in response to determining that the value of the media endurance metric of the block satisfies the media endurance metric criterion, the program operation on the block; determining whether a media health metric of the block satisfies a health threshold criterion; and adding, in response to determining that the media health metric of the block satisfies the health threshold criterion, the block to the exclusion list.

The invention belongs to the field of software model detection, and relates to an interrupt driver sequencing method based on staggered path splitting. Comprising the following steps: inputting a to-be-detected interrupt driver; selecting configuration parameters, and performing function inline preprocessing on the interrupt drive program according to the configuration parameters to obtain a bounded program without function call; staggered path splitting is realized by generating scheduling sequence configuration and code partition configuration, and part of configuration without atomic violation in a scheduling sequence and a code partition is deleted through an optimization process; inserting control codes in the original program according to different scheduling sequences and code partition combinations to generate a plurality of independent sequenced subprograms; executing parallel verification on the plurality of sequenced subprograms according to the number of processor cores in the configuration parameters; and outputting a verification result. According to the method, the large-scale program verification performance can be remarkably improved.

To provide a programming learning program. To create a programming learning program that allows users to easily and simply program using a commercially available personal computer without setting up a special programming environment, and to check the execution status of the computer programs they create. [Solution] A program used to verify the operation of a program created by the users themselves, characterized in that it contains an area for describing the created program.

A memory device includes a memory array having a plurality of memory cells. Control logic operatively is coupled with the memory array. The control logic receives a suspend command while programming multiple data states to a set of the plurality of memory cells of the memory array. The control logic determines whether a trim value associated with a program suspend operation is less than a total number of program verify operations to be performed during a present program verify loop of a programming operation. The control logic, in response to the trim value being less than the total number of program verify operations, causing only a subset of the total number of program verify operations that correspond to the trim value to be performed before causing a program suspend operation to be performed on the set of plurality of memory cells.

This application provides a chip verification method, apparatus, system, device, medium, and program. The verification method includes: simulating a chip, the chip including a program execution module and a memory storage module, the program execution module running a software program, and the program file of the software program being stored in the memory storage module; executing simulation test cases to cause the program execution module to call the program file for processing; monitoring read and write events of the memory storage module during the process of the program execution module calling the program file to track changes in variables of the software program, wherein the memory storage module has a memory area allocated for the variables of the software program; synchronizing and displaying the changes in the variables to reflect the running state of the software program, the running state being used to determine whether the processing of the software program by the program execution module meets the design expectations. The verification method provided by this application implements hardware and software co-simulation verification of the chip.

A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.

A processing device configures a memory device such that program verify operations are performed for each die of the memory device on different sub-blocks. In configuring the memory device, the processing device configures a first die for performance of program verify operations on a first sub-block within the first die and configures a second die for performance of program verify operations on a second sub-block within the second die. The processing device initiates a programming sequence to write data to the memory device based on the configuring of the memory device. The programming sequence comprises performance of a first program verify operation on the first sub-block within the first die prior to performance of a second program verify operation on the second sub-block within the second die.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

Technology for hybrid block management for dynamic SLC verify. The memory system tracks multi-level cell (MLC) programming speed of candidate pages in a three-dimensional NAND memory structure. The memory system determines whether each respective candidate page is eligible for single-level cell (SLC) programming without program verify based on the MLC programming speed. The memory system then programs the candidate pages based on the determination. The memory system may maintain a bitmap that specifies whether a particular candidate page is to receive program verify or not for SLC programming. In one aspect, the MLC programming speed is tracked by noting the number of program pulses used to complete MLC programming.

The invention aims to provide a multifunctional test module for program verification. The system comprises an MCU unit, the MCU unit is connected with a digital-to-analog converter, a digital multimeter, a pulse signal output and frequency reading unit, a main control chip and flash memory unit, and a pulse width modulation and time division multiplexing unit, the digital-to-analog converter outputs voltage, the voltage is amplified by an operational amplifier circuit and switched by an MUX switch, and the output voltage is converted into the output voltage. The analog-to-digital converter connected to the MCU unit is used for voltage reading, so that control program verification of the digital-to-analog converter and the analog-to-digital converter is realized; the digital multimeter is used for verifying various module programs; the pulse signal output and frequency reading unit outputs PWM signals through the MCU unit, the PWM signals pass through an operational amplifier follower circuit and a comparator, the output signals are connected to the MCU unit to be tested, and the PWM and FREQ program verification function is achieved. The invention is applied to the technical field of electronic test equipment.

The application relates to an authorization method and a storage medium for dynamically generating a License verification mode, which comprises the following steps: obtaining a feature code on a machine, and obtaining a License file through encryption; when a Java application is started, License information in the License file is read, key information in the read information is taken as a member variable name, and value information is taken as a member variable value and is stored in a class dynamically generated by bytecode; an authorization verification class for verifying the License information is generated through bytecode technology; the generated authorization verification class is instantiated, is transmitted into a Java application to generate a verification task, the information in the License file is verified, and if authorization fails, the current program is terminated. The code for verifying the License file is generated through bytecode, so even if a class file of the Java project is obtained, the code for verifying the License cannot be searched through the whole text by decompiling the class file.

A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. An offset value that is based on a loss level associated with the target wordline is selected. During a program verify operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline adjacent to the target wordline or a second wordline adjacent to the target wordline, where the pass through voltage level is a pass through read voltage level reduced by the offset value.

In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.

The application discloses a loop program termination judgment method based on a lexicographic neural rank function and belongs to the field of computer program verification. The method is aimed at a parallel assignment loop program and realizes automatic judgment on the termination of the loop program through the following steps of path extraction and condition construction, adaptive sampling, state transition dataset generation, neural rank function network construction and training of a variable lexicographic dimension, and counterexample guided verification. In the sampling stage, the application adopts an adaptive sampling strategy to avoid parameter sensitivity problems. In the network structure aspect, the application introduces a variable lexicographic dimension feedforward neural network to enhance the expression capacity of the rank function. In the verification stage, the application combines counterexample guidance and a multi-round training mechanism to improve the synthesis efficiency and success rate.

A method of runtime program verification receives recent values for a set of system health indicators of an external system through a preemptive mechanism of an operating system running on the external system. The recent value is compared to a calibration value for the set of system health indicators, and normal operation of the external system is verified based on whether a result of the comparison of the recent value to the calibration value is within a predetermined error threshold.

The application discloses a program verification metadata export method and device and a deterministic execution environment, and belongs to the field of compiling technology and formal verification. The method comprises the following steps: marking the pointer ownership state in the source code through attribute annotation; extracting the ownership conversion information and generating the structured metadata during compiling; and outputting the metadata to the special section of the compiling product, so that the memory safety of the program can be verified independently by directly reading the metadata by an external system. In order to make the exported metadata complete and inferable, a deterministic running environment composed of zero global state context, full-link memory management, capability token and deterministic execution suite is provided. In the application, specific attribute annotations in the source code are identified during the compiling process, the pointer ownership state conversion information and the function formal contract are generated into the structured metadata with a predefined binary format, and are written into the special metadata section of the target file (such as an ELF). In this way, the processing of the internal semantics of the program is changed from being internally digested and reformed by the compiler to being actively and standardized output to the external system, so that the technical obstacle that the program semantics information cannot be directly and reliably acquired by the external AI or verification tool is solved.

To increase performance, a non-volatile storage apparatus reduces the amount of time needed for program verify by eliminating a pause in the raising of word line voltages that has been used to allow the channels of memory cells to discharge. To compensate for the removal of the time previously used to allow the channels of memory cells to discharge without experiencing a disturb, a source line that is in communication with the channels is lowered from a source voltage applied to support programming to a source voltage applied to support sensing (for program verify) earlier than in previous designs such that the source line reaches the source voltage applied to support sensing (for program verify) prior to applying the verify reference voltage to the selected word line for program verify.

When a memory is considered to be relatively reliable, a data storage device can program the memory without performing a subsequent verify-read step. However, some memory cells may be known during the manufacturing of the data storage device to be difficult to program, and such memory cells can be identified in a predetermined list as requiring a verify-read step. Other memory cells may become difficult to program over time, and those memory cells can be identified in a dynamic list as requiring a verify-read step.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

The invention relates to the technical field of program verification, and discloses an auxiliary theorem generation and verification method for predicates in program verification, which comprises the following steps: S1, predicate branching: converting a definition of a given recursive predicate into a disjunctive normal form, and enabling each branch of the disjunctive normal form to be a combination of conjunctive sub-forms, and if the conjunct sub-formula of the disjunction branch contains the recursive call of the predicate, marking the branch as a recursive branch, otherwise, marking the branch as a termination branch. Through mode recognition and abstract interpretation, a verifier can flexibly process predicates defined by a user, and the applicability of a verification tool is improved; by intelligently analyzing a predicate structure and automatically generating an auxiliary theorem, the verification process is optimized, manual intervention is reduced, and the autonomous reasoning ability of a verifier is improved; and meanwhile, a mathematical induction method is converted into non-induction reasoning, so that the influence of a recursive structure on verification efficiency is reduced, and the reasoning process is more direct and efficient.

The invention relates to a security system and method for strongly binding a program and a hardware identifier, and belongs to the technical field of software protection and equipment authentication. According to the invention, an'authorization certificate 'uniquely bound with specific equipment is generated through a scheme of'encrypting a hardware identifier by a secret key derived from the hardware identifier'. The credential cannot be correctly decrypted and verified on any other hardware. When a protected program and an authorization certificate thereof are completely copied to another non-authorized device, due to different local hardware identifications of a new device, a correct decryption key cannot be generated when a program verification preamble module of the new device performs self-inspection, so that decryption fails and program operation is forcibly stopped, and therefore, pirate behaviors are effectively prevented.

The present disclosure provides an information processing apparatus that enables updating of a key for program verification without invalidating a program verification function. An information processing apparatus 1 that calculates a verification value using a key for program verification and that verifies whether the verification value matches a verification expected value stored in advance. The information processing apparatus 1 includes: a key updating control unit 12 that updates the key; a storage unit 100 that stores in advance a verification expected value corresponding to a key updated by the key updating control unit 12; and a verification expected value changing unit 13 that when a verification value calculated based on the updated key is verified, changes the verification expected value in the storage unit, the verification expected value being referred to for verification, to a verification value corresponding to the updated key.

A memory apparatus and operating method are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.