32 results about "Program validation" patented technology

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

The present application relates to managing programming convergence associated with memory cells of a memory sub-system. A first program pulse is caused to be applied to a word line associated with a memory cell of a memory sub-system. In response to the first program pulse, a program verify operation is caused to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sense node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sense node is identified. A bit line voltage matching the measured threshold voltage is caused to be applied to a bit line associated with the memory cell.

The invention belongs to the field of software model detection, and relates to an interrupt driver sequencing method based on staggered path splitting. Comprising the following steps: inputting a to-be-detected interrupt driver; selecting configuration parameters, and performing function inline preprocessing on the interrupt drive program according to the configuration parameters to obtain a bounded program without function call; staggered path splitting is realized by generating scheduling sequence configuration and code partition configuration, and part of configuration without atomic violation in a scheduling sequence and a code partition is deleted through an optimization process; inserting control codes in the original program according to different scheduling sequences and code partition combinations to generate a plurality of independent sequenced subprograms; executing parallel verification on the plurality of sequenced subprograms according to the number of processor cores in the configuration parameters; and outputting a verification result. According to the method, the large-scale program verification performance can be remarkably improved.

To provide a programming learning program. To create a programming learning program that allows users to easily and simply program using a commercially available personal computer without setting up a special programming environment, and to check the execution status of the computer programs they create. [Solution] A program used to verify the operation of a program created by the users themselves, characterized in that it contains an area for describing the created program.

This application provides a chip verification method, apparatus, system, device, medium, and program. The verification method includes: simulating a chip, the chip including a program execution module and a memory storage module, the program execution module running a software program, and the program file of the software program being stored in the memory storage module; executing simulation test cases to cause the program execution module to call the program file for processing; monitoring read and write events of the memory storage module during the process of the program execution module calling the program file to track changes in variables of the software program, wherein the memory storage module has a memory area allocated for the variables of the software program; synchronizing and displaying the changes in the variables to reflect the running state of the software program, the running state being used to determine whether the processing of the software program by the program execution module meets the design expectations. The verification method provided by this application implements hardware and software co-simulation verification of the chip.

A request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. The program operation is performed using the modified sensing time period during a program verify phase of the program operation.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

The invention discloses a complex program verification method based on nonlinear constraint local search solution, which belongs to the technical field of computer program verification, and comprises the following steps: generating an SMT-NRA formula of a program to be verified based on a verification target; constructing a linear equation set based on linear equality constraints in the formula, and performing replacement from non-free variables to free variables by solving the equation set to obtain a simplified formula; heuristic initialization based on a divide-and-conquer strategy is carried out on the simplified formula; an initial assignment value is obtained through standard random initialization and short-time search solution, or local search solution is carried out by dividing sub-formulas; performing iterative search on the initial assignment based on multi-path parallelism and adaptive neighborhood limitation; maintaining a multi-path list, adaptively determining candidate moving directions in each round, and allocating the candidate moving directions to each path to update the assignment; and judging the property of the to-be-verified program according to a final result of the iterative search and outputting a conclusion. According to the invention, efficient verification of the key program module containing complex nonlinear logic is realized.

The application discloses a loop program termination judgment method based on a lexicographic neural rank function and belongs to the field of computer program verification. The method is aimed at a parallel assignment loop program and realizes automatic judgment on the termination of the loop program through the following steps of path extraction and condition construction, adaptive sampling, state transition dataset generation, neural rank function network construction and training of a variable lexicographic dimension, and counterexample guided verification. In the sampling stage, the application adopts an adaptive sampling strategy to avoid parameter sensitivity problems. In the network structure aspect, the application introduces a variable lexicographic dimension feedforward neural network to enhance the expression capacity of the rank function. In the verification stage, the application combines counterexample guidance and a multi-round training mechanism to improve the synthesis efficiency and success rate.

The application discloses a program verification metadata export method and device and a deterministic execution environment, and belongs to the field of compiling technology and formal verification. The method comprises the following steps: marking the pointer ownership state in the source code through attribute annotation; extracting the ownership conversion information and generating the structured metadata during compiling; and outputting the metadata to the special section of the compiling product, so that the memory safety of the program can be verified independently by directly reading the metadata by an external system. In order to make the exported metadata complete and inferable, a deterministic running environment composed of zero global state context, full-link memory management, capability token and deterministic execution suite is provided. In the application, specific attribute annotations in the source code are identified during the compiling process, the pointer ownership state conversion information and the function formal contract are generated into the structured metadata with a predefined binary format, and are written into the special metadata section of the target file (such as an ELF). In this way, the processing of the internal semantics of the program is changed from being internally digested and reformed by the compiler to being actively and standardized output to the external system, so that the technical obstacle that the program semantics information cannot be directly and reliably acquired by the external AI or verification tool is solved.

When a memory is considered to be relatively reliable, a data storage device can program the memory without performing a subsequent verify-read step. However, some memory cells may be known during the manufacturing of the data storage device to be difficult to program, and such memory cells can be identified in a predetermined list as requiring a verify-read step. Other memory cells may become difficult to program over time, and those memory cells can be identified in a dynamic list as requiring a verify-read step.

Methods, systems, and devices for configurable program verify levels according to PECs at a memory system are described. The described techniques provide for a memory system to adjust a program verify offset magnitude when performing a program verify operation on a memory cell according to a program-erase cycle (PEC) count of the memory cell. For example, due to higher PEC counts being associated with relatively higher charge loss rates, the memory system may apply a relatively higher program verify offset to the memory cell when the PEC count of the memory cell is relatively high and may apply a relatively lower program verify offset to the memory cell when the PEC count of the memory cell is relatively low.

The invention relates to a security system and method for strongly binding a program and a hardware identifier, and belongs to the technical field of software protection and equipment authentication. According to the invention, an'authorization certificate 'uniquely bound with specific equipment is generated through a scheme of'encrypting a hardware identifier by a secret key derived from the hardware identifier'. The credential cannot be correctly decrypted and verified on any other hardware. When a protected program and an authorization certificate thereof are completely copied to another non-authorized device, due to different local hardware identifications of a new device, a correct decryption key cannot be generated when a program verification preamble module of the new device performs self-inspection, so that decryption fails and program operation is forcibly stopped, and therefore, pirate behaviors are effectively prevented.

The present disclosure provides an information processing apparatus that enables updating of a key for program verification without invalidating a program verification function. An information processing apparatus 1 that calculates a verification value using a key for program verification and that verifies whether the verification value matches a verification expected value stored in advance. The information processing apparatus 1 includes: a key updating control unit 12 that updates the key; a storage unit 100 that stores in advance a verification expected value corresponding to a key updated by the key updating control unit 12; and a verification expected value changing unit 13 that when a verification value calculated based on the updated key is verified, changes the verification expected value in the storage unit, the verification expected value being referred to for verification, to a verification value corresponding to the updated key.

This invention provides a method for performing programming operations in a memory device and a memory device itself. [Solution] The memory device 100 includes a memory array 126 having a memory block having a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The memory device also includes a control circuit 110 having a programming circuit that programs the memory cells of a selected word line from the plurality of word lines into a plurality of data states in a plurality of program loops including programming pulses and verification operations. The circuit does not lock out a set of the plurality of NAND strings during at least one of the verification operations. The NAND strings of the set include at least some of the memory cells of the selected word line that have completed programming so that electricity conducts through the NAND strings of the set during sensing.

To provide a detection system that makes it possible to detect partial discharges even if measurement data includes noise that differs depending on the environment, a parameter update system, a detection program, a verification server, a verification method, and a verification program.SOLUTION: The detection system includes an acquiring unit, a processing unit, a determining unit, and an updating unit. The acquiring unit acquires measurement data from a sensor attached to a power device to be monitored. The processing unit processes the measurement data on the basis of parameters associated with the power device. The determining unit determines whether a partial discharge is occurring in the monitored target on the basis of the processed measurement data. The updating unit updates the parameters on the basis of the same determination result on whether partial discharge is occurring among a plurality of pieces of reference measurement data, which is measurement data acquired in the past.SELECTED DRAWING: Figure 1

The application provides a program processing method for reducing the difficulty of data structure formal verification, which comprises the following steps: firstly, the complex data structure is described by a nested shape graph; then, the shape definition of the final nested shape graph is obtained by analyzing the shape definition of the main data structure and the secondary data structure; then, the predicate and macro definition containing the universal quantification assertion in the assertion are expanded, all the assertions are traversed and matched based on the deductive reasoning, and the new assertion is obtained by splitting and splicing according to the matching result. The application adopts the splitting and splicing mode for the complex data structure program with the universal quantification assertion, greatly reduces the complexity of the formal verification, effectively reduces the difficulty of the data structure program verification, and improves the verification efficiency.

Technology for hybrid block management for dynamic SLC verify. The memory system tracks multi-level cell (MLC) programming speed of candidate pages in a three-dimensional NAND memory structure. The memory system determines whether each respective candidate page is eligible for single-level cell (SLC) programming without program verify based on the MLC programming speed. The memory system then programs the candidate pages based on the determination. The memory system may maintain a bitmap that specifies whether a particular candidate page is to receive program verify or not for SLC programming. In one aspect, the MLC programming speed is tracked by noting the number of program pulses used to complete MLC programming.

Methods, systems, and devices for techniques for performing a read operation for memory cells are disclosed herein. A word line voltage level is ramped at a first rate of change. Memory cell activation outputs are detected from a subset of the memory cells based on ramping the word line voltage level at the first rate of change. Word line read levels are calibrated for the memory cells based on the detected memory cell activation outputs. The word line voltage level is ramped at a second rate of change, and data stored in the memory cells activated is read when the word line voltage level ramped at the second rate of change reaches the calibrated word line read levels. A reset program verify operation is not applied to memory cells corresponding to at least one stage of the word line based on previously applied programming pulses or program verify operations.

The present disclosure provides a platform for compiling programs and a method for compiling application programs, and relates to the technical field of computers. The specific implementation scheme is as follows: the platform for compiling programs comprises an environment module, a core module and a packaging container module; the environment module is used for setting a platform software system version and a platform compiling environment version according to a compiling instruction and first configuration information, completing platform environment building; the core module is used for caching platform programs and, in the case that the platform programs are not stored in a local cache, acquiring the platform programs from a first target server according to second configuration information, and further used for performing a compiling operation on the platform programs to obtain a first target program; and the packaging container module is used for program verification and output of the first target program. According to the scheme of the present disclosure, the corresponding version of the platform environment can be adaptively built based on the compiling instruction, the required compiling programs can be cached, the cached programs can be acquired from any server, and the compiling programs can be verified, thus breaking the physical limitation of software and hardware isolation.

To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.

The invention belongs to the field of software model detection, and relates to a correctness verification method for a serialization-based unbounded interrupt driver. An interrupt driving program is converted into a sequenced program by using a sequenced technology, global auxiliary variables such as a program counter, a control mode variable and a shielding variable are introduced, random context switching, multi-stage interrupt nesting and interrupt shielding behaviors are simulated by means of macro and execution modes, and the obtained sequenced program is detected by using a model detection tool CBMC or CPAchecker. And verifying the correctness of the unbounded interrupt driver. According to the method, an interrupt driving program is converted into an equivalent sequential execution program, and all possible execution interlaced paths are accurately simulated, so that the correctness of the program can be effectively verified, and particularly under the condition of complex behaviors such as interrupt nesting, multi-stage interrupt, priority scheduling and interrupt shielding, the execution efficiency of the program is greatly improved. And the problems of state space explosion and false positive in a traditional model detection method can be avoided.

This application discloses a program verification method, apparatus, device, and storage medium, belonging to the field of software technology, which can solve the problem of inaccurate detection of real-time security of programs. The method includes: obtaining an intermediate representation of the program to be analyzed through a static analyzer; initially coloring the function nodes corresponding to the real-time context in the intermediate representation according to preset external semantic rules to obtain basic nodes; constructing a function call relationship graph based on the function information of the program to be analyzed; color propagating on the function call relationship graph based on the basic nodes to color the function nodes on the call paths corresponding to the basic nodes; and performing a blocking determination on the function nodes when the color of the function nodes in the call relationship graph indicates that the function nodes have non-real-time security attributes.

A method for programming data in a memory device is described herein. The method includes providing a programming pulse via a controller to each of a plurality of word-lines in each of a plurality of sub-blocks of each of a plurality of planes of the memory device. The method further includes providing a verification pulse via the controller selectively to a set of the word-lines in one or more of the sub-blocks of a proper subset of the planes of the memory device.

A method may include: a broadcaster computer program generating, for participants in a network in a transaction, a commit, an audit token, and a proof of consistency; the broadcaster computer program broadcasting, the commits, the audit tokens, and the proofs of consistency for each participant to all participants in the network; the participant computer programs generating complimentary commits, complimentary audit tokens, complementary proofs of consistency, proofs of equivalency, and a proof of assets; the broadcaster computer program receiving from each of the participant computer programs, the proof of assets, the complimentary commit, the complimentary audit token, the complementary proof of consistency, and the proof of equivalency; the broadcaster computer program and / or the participant computer programs verifying, the proofs of assets, the proofs of balance, the proofs of consistency, and the proofs of equivalency; and the broadcaster computer program approving the transaction based on the verification.

Methods, systems, and devices for techniques for performing a read operation for memory cells are disclosed herein. A word line voltage level is ramped at a first rate of change. Memory cell activation outputs are detected from a subset of the memory cells based on ramping the word line voltage level at the first rate of change. Word line read levels are calibrated for the memory cells based on the detected memory cell activation outputs. The word line voltage level is ramped at a second rate of change, and data stored in the memory cells activated is read when the word line voltage level ramped at the second rate of change reaches the calibrated word line read levels. A reset program verify operation is not applied to memory cells corresponding to at least one stage of the word line based on previously applied programming pulses or program verify operations.

The application discloses a kind of based on Docker's Internet of Things program runtime verification method, it is related to program verification technical field, the method includes: based on integrity measurement architecture, container image is hashed and is measured and is written into measurement list;The measurement value in the measurement list corresponding to target container is stored to the vPCR module corresponding to target container;vPCR module is extended into trusted platform module;The identity information and state information of the host platform where target container is located are verified, and the container is successfully started if the verification is passed;According to container ID, target container inner process pid and acquisition time, the memory binary information of corresponding process runtime is acquired, and memory event is constructed;The memory event corresponding to the verification of business flow on Internet of Things program of the memory event on the state machine end received by inter-state flow is realized. The application improves the security of Internet of Things program running.