Correctness verifying method of cache consistency protocol

Abstract

The invention provides a correctness verifying method of a cache consistency protocol. After a computer enters an operating system, the complexity of a core and the application of the operating system is higher; the action of a processor is not easy to control accurately; therefore, in order to keep verification correctness, a verifying program for the cache consistency protocol is necessary to embed in a systematic procedure; the program is embedded in a BIOS (basic input/output system) code; after the initialization of a memory subsystem is completed at the initialization initial stage of the system, the verifying program is started to be executed; the verifying program needs to be capable of accurately controlling actions of each processor of the system, supports a user to select a verification item to be particularly executed, and feeds back a verification result to the user; by using the method, the verification of the correctness of the cache consistency protocol is realized at a system level; all application scenes of a real system can be completely covered; the disadvantages that a conventional verifying method based on an analog way is low in efficiency and poor in verification coverage rate are made up; the design period and the verifying period of an inter-domain cache consistency chip of the processor can be shortened; the one-time taping-out mission success rate of the chip can be guaranteed effectively; and therefore, the correctness verifying method has an extremely wide development prospect and an extremely high technical value.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a method for verifying the correctness of a cache consistency protocol. Background technique [0002] The adoption of cache technology is related to the increasing speed of processors. As the speed of the processor continues to increase, there is a contradiction between the access speed of the memory and the speed of the processor. In order to solve the contradiction between the two, a cache is introduced, which is located between the processor and the memory to match the speed between the two, so that the system has the speed of the cache and the capacity of the main memory from the perspective of the CPU. However, after the introduction of the cache technology, another problem is also introduced, that is, the consistency of the cache. [0003] At this stage, with the development of multi-processor, multi-core, and many-core technologies, data inconsistency may occur between...

AI Technical Summary

Problems solved by technology

[0005] As the core component of a large-scale CC-NUMA system, the chip that maintains the cache consistency between processor domains is extremely complicated to design and verify. Often, due to insufficient verification work in the early stage, the chip fails to be put into a single chip, and multiple shots are required. Repeatedly, this greatly increases the cost of chip design and seriously affects the development cycle

The current common practice in the industry is to use simulation to perform protocol-level verification, but this verification method is inefficient and it is difficult to guarantee that all scenarios can be traversed

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