Debugging system

Abstract

In a debugging system for use in realizing simultaneously complete observation of internal operation and reproduction of malfunction actually caused in a target system which includes an integrated circuit, such as a microprocessor, contents of a memory and an internal initial state of the target system are snooped and stored in a snoop unit and a trace memory, respectively, both of which are included in a probe unit attached to the target system. The internal operation and the reproduction are simulated by a software simulator model by the use of the contents and the internal initial state which are stored in the trace memory and which are sent from the probe unit.

Description

1. Field of the InventionThe present invention relates to a debugging system for use in analyzing operation in various kinds of systems, such as an LSI system which include a microprocessor and, in particular, to a software simulator. Such systems may be, for example, a system which uses a digital synchronizing circuit wherein internal operation can not be directly monitored, a system including an interface which is located between synchronizing circuits and wherein direct monitoring of operation is difficult, or a system using an asynchronous interface such as a serial interface, a high speed bus interface or the like between synchronizing circuits.2. Description of Related ArtIn general, it is a recent trend that not only a single function but also a plurality of functions are incorporated in one chip in a functional LSI represented by a microprocessor with development of the micro fabrication technology. This enables a high speed operation of the system, a multifunction of the sy...

AI Technical Summary

Problems solved by technology

Recently, the system tends to become very large and complicated.

This renders software and hardware into very large sizes and makes debugging difficult more and more.

As a result, it becomes difficult to observe behavior executed in connection with an instruction, by the use of an external terminal of the LSI chip.

Under the circumstances, this structure make it difficult to analyze behavior of the timer, the serial interface, and the like from an external device and also makes it very difficult to execute debugging operation concerned with these elements.

However, when the cache memory is kept in an active state, contents followed by execution of an instruction cannot be monitored by the trace analyzer 703.

Meanwhile, in a branch operation where an address is dynamically determined, estimation of the operation is not feasible only by these terminals.

However, the stoppage of the operation makes it actually impossible to observe an actual system in real time.

However, it is difficult to find out a cause of a malfunction only by the flow of the instructions, although the flow of the instructions give a clue for grasping the behavior of the system.

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