54 results about "Texel" patented technology

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a first comparator, a first divider, a first summator and a texel adjusting unit. A first comparator to determine a first value, the first value being determined based on a smaller value of the integer portion of the input texture coordinate and the maximum offset; the first divider is used for calculating a ratio between the input offset and the first divisor to obtain a first ratio; the first summator is used for calculating the quotient of the first ratio and the sum of the first numerical value and the second numerical value to obtain a first calculation result; and the texel adjusting unit is used for determining a target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and the addressing mode. According to the method, the first calculation result can be determined based on the smaller value in the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

In various examples, a simulation platform generates a simulated driving environment by processing road map data to derive the location of wear-related visual artifacts for sections of a lane surface. Using map data, the simulation platform generates texture maps for aesthetic road rendering, which are used to apply textures to a 3D polygon topology mesh. The simulation platform generates visual artifacts representing the wear and tear of the road surface based on a calculation of one or more lane feature distances derived from the map data. The simulation platform calculates distances associated with reference line data derived from an image to render a texture of one or more lane features.The spacing is used to determine how the appearance of the texel is adjusted to include wear-related visual artifacts when displayed on a lane of the simulated driving environment.

Proximity-based surface texture generation for simulated environment systems and applications is disclosed. In various examples, a simulation platform generates a simulated driving environment by processing road map data to infer locations of wear-related visual artifacts for portions of a roadway surface. The simulation platform uses the map data to generate texture maps for aesthetic road rendering, which are used to apply texture to the 3D polygon topology mesh. The simulation platform generates visual artifacts representing use and wear of the roadway surface based on calculating one or more distances from roadway lane features derived from the map data. The simulation platform calculates a distance from the one or more roadway lane features associated with reference line data derived from the image to render the texture. The distances are used to determine how to adjust the appearance of texels to include wear-related visual artifacts when rendering wear-related virtual artifacts on the roadway of the simulated driving environment.

Techniques are disclosed relating to texture accesses by a graphics processor. In some embodiments, shader processor circuitry executes a multi-fetch instruction that specifies an access location and shape information for a thread and return sequence information that indicates an ordering of return data for the multi-fetch instruction. Based on the multi-fetch instruction and the shape information, texture processor circuitry may access multiple texels of a surface stored by the texture storage circuitry (where a plurality of the multiple texels are accessed at least partially in parallel) and provide the accessed multiple texels to the shader processor circuitry for the thread, over multiple clock cycles, according to the ordering specified by the return sequence information. Disclosed techniques may advantageously improve texture sampling throughput, particularly in the absence of filtering samples.

Disclosed approaches provide for interactions of secondary rays of light transport paths in a virtual environment to share lighting contributions when determining lighting conditions for a light transport path. Interactions may be shared based on similarities in characteristics (e.g., hit locations), which may define a region in which interactions may share lighting condition data. The region may correspond to a texel of a texture map and lighting contribution data for interactions may be accumulated to the texel spatially and / or temporally, then used to compute composite lighting contribution data that estimates radiance at an interaction. Approaches are also provided for reprojecting lighting contributions of interactions to pixels to share lighting contribution data from secondary bounces of light transport paths while avoiding potential over blurring.

Techniques are disclosed relating to texture sampling, e.g., in graphics processors. In some embodiments, a device includes processor circuitry (e.g., shader pipelines) configured to execute graphics programs and multiple sample pipelines. A given sample pipeline may be configured to, for a multi-texel sample operation specified by the processor circuitry, access texel data for multiple texels forming a first shape in a texture (e.g., a 2×2 square) and perform one or more filter operations to generate a result for the multi-texel sample operation. Point sample control circuitry may be configured to detect that multiple point sample operations, specified by the processor circuitry, access a set of texels having the first shape. The point sample control circuitry may assign the multiple point sample operations to one of the sample pipelines for performance in parallel by the sample pipeline and provide results of the assigned multiple point sample operations to the processor circuitry.

A ray emission region perpendicular to a normal direction of a sampled texel in a first mesh patch of a first initial three-dimensional mesh model in a three-dimensional virtual scene is constructed. One or more rays that start in the ray emission region and extend in an opposite direction of the normal direction of the sampled texel are constructed. One or more candidate texels that intersect with the one or more rays are determined. When the one or more candidate texels include at least one spatially adjacent texel of the sampled texel, the sampled texel is determined as a first seam texel. From the at least one spatially adjacent texel, a second seam texel having a seam adjacency relationship with the first seam texel is determined. At least a seam repair of the first seam texel and the second seam texel is performed to obtain a target three-dimensional mesh model.

Certain aspects of the present disclosure provide techniques for reconstructing a texel of a texture. Such techniques may include receiving a plurality of sets of features corresponding to the texture, wherein the plurality of sets of features comprises a respective set of features for each respective grid point of a grid; receiving coordinate information corresponding to the texel of the texture; receiving level of detail information; selecting a subset of grid points of the grid based on the second resolution being lower than the first resolution; sampling one or more grid points from among the subset of grid points based on the coordinate information to obtain sampled features associated with the one or more grid points; inputting, to a machine-learning model, the sampled features; and receiving, from the machine-learning model, based on the sampled features, a reconstruction of the texel of the texture at the second resolution.

In disclosed embodiments, compression circuitry may compress data blocks and compressed write data blocks and corresponding compression metadata to a certain level in a cache / memory hierarchy. In some embodiments, the compression circuitry is configured to detect a pre-determined set of data values in a block of data to be compressed. In response, the compression circuitry may write a special metadata value for the data block to data storage circuitry to indicate compression of the data block, without writing a compressed version of the data block to the data storage circuitry. This may advantageously improve performance and reduce power consumption for data blocks with certain data values (e.g., having uniform pixel / texel values).

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a multiplier, a first divider, a first adder, a second adder and a texel adjusting unit, the multiplier is used for calculating the product of the decimal part of the input texture coordinate and the texture size to obtain a first numerical value; the first divider is used for calculating a first ratio between the input offset and the second value; the first summator is used for determining a first calculation result according to the integer part of the input texture coordinate and the first ratio; the second summator is used for determining a second calculation result according to the first numerical value and the first ratio; and the texel adjusting unit is used for determining a texel index corresponding to the input texture coordinate according to the first calculation result and the second calculation result. According to the method, a single calculation unit only needs to calculate partial data of the input texture coordinates, so that the bit width of the calculation unit is effectively reduced, and the complexity of physical implementation of the calculation unit is reduced.

The application provides a texture memory bank read access optimization system and optimization method, conflict detection is performed on generated 16-way texture addresses, texture addresses accessing the same texture block are composed into address groups, a plurality of address groups are obtained, a conflict flag of each address group and an effective texel mark bit in the group are generated, and an access request and the conflict flag are sent to a corresponding storage unit Bank in parallel according to each address group; when each storage unit Bank receives the access request, corresponding texture block data is returned, and a data assembly module reads corresponding texel data from the corresponding texture block data in parallel according to the effective texel mark bit in each address group. The application performs feature comparison conflict detection on texture addresses in parallel, groups the texture storage unit Bank, and then outputs in parallel, without preprocessing, and is not coupled with other parts in the texture unit, and is easy to implement; and the design mode of the pipeline is adopted, and the execution efficiency is high.

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a multiplier used for calculating a product of a mantissa of an input texture coordinate in a floating-point number format and a texture size to obtain a first product; the first conversion unit is used for leftwards shifting the input offset by N bits to obtain the shifted input offset; the adder is used for calculating the sum of the first product and the shifted input offset to obtain a first calculation result; the second conversion unit is used for rightwards shifting the first calculation result by M bits to obtain a shifted first calculation result; based on the shifted first calculation result and the rounding mode, a second calculation result is obtained, and the second calculation result is used for determining a texel index corresponding to the input texture coordinates. According to the method, the second calculation result in the preset fixed-point format can be obtained only by executing the unified right-shift operation once, and the number of times of the right-shift operation is reduced, so that the determined texel index is more accurate.

A processor receives a request to access one or more levels of a portion of a persistent texture (PRT) resource. The levels represent textures at different levels of detail (LODs) and the request includes normalized coordinates indicative of a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more persistent maps indicative of texels that are resident in the PRT resource. The processor converts the normalized coordinates to texel coordinates in the one or more persistent maps based on the offsets and accesses the one or more persistent maps based on the texel coordinates in response to the request to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

A method of operation of a texturing / shading unit in a GPU pipeline is used for efficient convolution operations. The method uses texture hardware to collectively fetch all the texels required to calculate properties for a group of output pixels without any duplication. The method then bypasses bilinear filter hardware in the texture hardware and passes the fetched and unfiltered texel data from the texture hardware unit to shader hardware in the texturing / shading unit. The shader hardware uses the fetched texel data to perform a plurality of convolution operations to calculate the properties of each of the output pixel.

The disclosed method for rendering graphic images includes, for each lane contained in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane contained in the plurality of lanes, computing a filtered value based on a plurality of the texel samples read from a corresponding plurality of lanes, based on a footprint associated with the lane; and rendering at least one section of a graphic image based on the filtered values ​​computed for the plurality of lanes.

Systems and methods are disclosed for training and using a digital human foundational model (DHFM) comprising a generative adversarial network (GAN) generator. For instance, the method may include obtaining one or more inputs comprising pose information indicating a three-dimensional (3D) pose representation of a human and processing the one or more inputs using a mapping network to generate intermediate latent code. The method may further include processing the intermediate latent code using the trained generator to generate texel-aligned Gaussian maps that align Gaussian attributes to a coarse mesh template of the human and performing linear blend skinning and deformation on the texel-aligned Gaussian maps to obtain modified texel-aligned Gaussian maps. The method may also include processing the modified texel-aligned Gaussian maps using a multi-part renderer to generate a synthetic human representation of the human indicating facial and hand features of the human.

Certain aspects of the present disclosure provide techniques for reconstructing a texel of a texture. Such techniques may include receiving a plurality of sets of features corresponding to the texture, wherein the plurality of sets of features comprises a respective set of features for each respective grid point of a grid; receiving coordinate information corresponding to the texel of the texture; receiving level of detail information; selecting a subset of grid points of the grid based on the second resolution being lower than the first resolution; sampling one or more grid points from among the subset of grid points based on the coordinate information to obtain sampled features associated with the one or more grid points; inputting, to a machine-learning model, the sampled features; and receiving, from the machine-learning model, based on the sampled features, a reconstruction of the texel of the texture at the second resolution.

A decoder is configured to decode a plurality of texels of a p by q sub-block of texels from a block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format. The b

A graphics processor includes a texel unit and an execution unit. The texel unit includes a loading module. The execution unit includes an im2col module to execute an im2col algorithm to expand an original matrix to obtain an expansion matrix according to the size of a kernel. The execution unit multiplies the expansion matrix and the kernel to obtain a feature map matrix. The loading module calculates feature coordinates of each element of the feature map matrix according to the coordinates of the expansion matrix, and obtains the original coordinates of each element of the original matrix according to the feature coordinates, the size of the kernel, a stride, and padding. The loading module reads at least one of the memory blocks covered by the original coordinates of each element of the original matrix, and outputs data corresponding to the original coordinates in the memory blocks.

A method of rendering a frame showing a scene formed by primitives in a tile-based graphics processing system includes a geometry processing phase tiling the primitives in the scene, to determine which primitives at least partially overlap which tiles of the frame to be rendered. A rendering phase obtains a fragment density map defining one or more texels, each texel corresponding to an area of the frame to be rendered and having an associated fragment size, wherein for each of the texels, the texel's height is an integer multiple of a native tile height used in the tile-based graphics processing system and the texel's width is an integer multiple of a native tile width used in the tile-based graphics processing system. The rendering phase also determines from the fragment density map a fragment size to be used to render the tile, performing sampling using the determined fragment size and performing fragment shading using the determined fragment size.

The disclosed method for rendering graphic images includes, for each lane contained in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane contained in the plurality of lanes, computing a filtered value based on a plurality of the texel samples read from a corresponding plurality of lanes, based on a footprint associated with the lane; and rendering at least one section of a graphic image based on the filtered values ​​computed for the plurality of lanes.

The invention relates to the field of computer graphics, in particular to a highlight primitive drawing method and device and a storage medium. The method comprises the following steps: creating a plurality of texels according to a basic drawing, wherein the texels are in one-to-one correspondence with pixels in the basic drawing; each texel comprises a plurality of counting units, and different counting units are used for recording response times of different highlight patterns; in response to the primitive highlight display operation, determining a highlight primitive and a highlight style corresponding to the highlight primitive from the basic drawing; determining a target texel according to the pixels covered by the highlight primitives; determining a target counting unit in the target texel according to a highlight style corresponding to the highlight primitive, and updating the response frequency recorded by the target counting unit; on the basis of the design parameters of the different highlight styles, highlight display features of all texels are determined according to the response times; and according to a corresponding relation between texels and pixels, mixing the ontology display features and the highlight display features to obtain a target drawing. And the drawing refreshing efficiency is optimized, and the highlight effect is refined.

Performing texel access operations on multiple texels responsive to executing a single instruction by graphics processing units (GPUs) is disclosed herein. In some aspects, a GPU is configured to, responsive to execution of a single instruction, determine a first coordinate and a second coordinate of a location of a first texel of a texture. The GPU is further configured to determine a first offset corresponding to the first coordinate of the first texel and a second offset corresponding to the second coordinate of the first texel. The GPU is also configured to perform a texel access operation on each of the first texel and a second texel of the texture, wherein a location of the second texel is represented by a first sum of the first coordinate and the first offset, and a second sum of the second coordinate and the second offset.

The disclosed method for rendering graphics images includes, for each lane included in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane included in the plurality of lanes, computing a filtered value based on a plurality of the texel samples that are read from a corresponding plurality of lanes based on a footprint associated with the lane; and rendering at least one portion of a graphics image based on the filtered values computed for the plurality of lanes.

A method for generating metadata to accompany a volumetric video for texels in an object in a volumetric video. The method comprises steps of: inputting a 2D representation of the object; identifying areas in the representation that have the same one or more properties with respect to light; and generating input material groups, where all texels in each input material group have the same properties with respect to light. There exists a correspondence between at least part of the input representation and at least part of the object in the volumetric video, so that there is a correspondence between texels in the representation and texels in the object so that output material groups can be generated from the input material groups and the properties with respect to light can be stored with the volumetric video as metadata.

The application discloses an ALU, a processor, a chip, a device and a texel index calculation method, and belongs to the chip technical field. The ALU comprises a multiplier, a first divider, a first adder, a second adder and a texel adjustment unit. The multiplier is used for calculating the product of the decimal part of input texture coordinates and the texture size to obtain a first value. The first divider is used for calculating the first ratio between the input offset and the second value. The first adder is used for determining the first calculation result according to the integer part of the input texture coordinates and the first ratio. The second adder is used for determining the second calculation result according to the first value and the first ratio. The texel adjustment unit is used for determining the texel index corresponding to the input texture coordinates according to the first calculation result and the second calculation result. According to the above method, only part of the data of the input texture coordinates needs to be calculated in a single calculation unit, the bit width of the calculation unit is effectively reduced, and the complexity of the physical implementation of the calculation unit is reduced.

The invention provides a texture filtering testing method and device, equipment and a medium, and belongs to the technical field of testing. The texture filtering test method comprises the following steps: determining a combined filtering mode according to a plurality of single filtering modes supported by a to-be-tested unit; determining combined counting information corresponding to the combined filtering mode according to target texel attribute information corresponding to the to-be-detected texture data and single counting information of each single filtering mode corresponding to the combined filtering mode; according to the combined filtering mode, the combined counting information and the to-be-detected texture data, obtaining input data of the to-be-detected unit; the to-be-tested unit is tested based on the input data, a test result of the to-be-tested unit is obtained, and the test result is used for representing whether the to-be-tested unit passes the texture filtering test or not. According to the embodiment of the invention, the number of test cases can be reduced, and the test efficiency is improved.

In various examples, a simulation platform generates a simulated driving environment by processing road map data to infer the location of wear-related visual artifacts for portions of a roadway surface. Using map data, the simulation platform generates texture maps for aesthetic road renderings that are used to apply textures onto a 3D polygon topology mesh. The simulation platform generates visual artifacts representing use and wear of the roadway surface based on calculating one or more distances from roadway lane features derived from the map data. The simulation platform computes distances associated with reference line data derived from an image to render texture from one or more roadway lane features. The distances are used in determining how the appearance of the texels are adjusted to include the wear-related visual artifacts when rendered on a roadway of the simulated driving environment.

The embodiment of the invention provides a scene rendering method and device, equipment and a storage medium. The method comprises the following steps: determining a corresponding visible texel set according to a mapping texel point of each pixel point in a current to-be-rendered frame in a target texture image of a specified rendering scene; the visible texel sets are reported to a server side, so that the server side combines the visible texel sets reported by multiple terminals into a visible texel union set, and the visible texel union set is issued to each terminal through a reference texture image subjected to texture rendering; and according to the reference texture image, rendering the current to-be-rendered frame and then displaying the current to-be-rendered frame. According to the embodiment of the invention, one-time efficient texture rendering and texture rendering multiplexing of multiple terminals in the texture space for the specified rendering scene can be realized, the repeated texture rendering overhead of the multiple terminals for each rendering of the specified rendering scene is greatly reduced, and the rendering frame rate and smooth display of each terminal for the specified rendering scene are improved.