56 results about "Texel" patented technology

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate / data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate / data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate / data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle / stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle / stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.

A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

The invention provides a graphics processor and an acceleration method thereof. The graphics processor comprises a texel unit and an execution unit. The texel unit comprises a reading module. The execution unit comprises: an im2col module which is used for executing an im2col algorithm and expanding an original matrix according to the size of a convolution kernel to obtain an expanded matrix; an execution unit which multiplies the extended matrix by the convolution kernel to obtain a feature matrix; a reading module which calculates a characteristic coordinate of each element of the characteristic matrix according to the coordinate of the extended matrix, and obtains an original coordinate of each element of the original matrix according to the characteristic coordinate, the convolution kernel, the pace value and the filling value, wherein the reading module reads at least one of the storage blocks covered by the original coordinates of each element of the original matrix, and transmits data corresponding to the original coordinates in the at least one of the storage blocks to the im2col module.

An array (1) of texture data elements (texels) is subdivided into a plurality of 8 x 4 texture element blocks (2), each of which 8 x 4 texture element blocks (2) encodes two 4 x 4 texture element sub-blocks (3, 4). Each encoded texture data block (5) includes data indicating a method to be used to generate a set of colour values to be used for the texture elements that the encoded data block (5) represents, and data indicatin a method to be used for generating the colours of the individual texture elements using that generated set of colours. As well as the individual texture data blocks (5), a header data block encoding a base set of colours is generated. This base colour set defines a set of colours that is used to generate the colours to be used when reproducing each individual encoded texture data block (5).

A computer graphics rendering apparatus according to an embodiment of the present invention generates a screen image, using plural texture images having different mipmap levels. The apparatus generates a normalized texture coordinate of a texture image, generates, from the normalized texture coordinate of the texture image, a texel coordinate of a texel in the texture image, according to a mipmap level of the texture image, and generates, regarding an image block in the texture image, an index value indicating a cache line corresponding to the image block, using a texel coordinate of a texel in the image block. The apparatus generates the index value such that index values of image blocks in the same position are different, between two texture images having mipmap levels adjacent to each other.