Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Cache architecture for efficiently accessing texture data using buffers

A technology for caching and texture data, applied in memory systems, electrical digital data processing, instruments, etc.

Active Publication Date: 2017-09-12
SAMSUNG ELECTRONICS CO LTD
View PDF6 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are many disadvantages and limitations associated with traditional texture caching schemes

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cache architecture for efficiently accessing texture data using buffers
  • Cache architecture for efficiently accessing texture data using buffers
  • Cache architecture for efficiently accessing texture data using buffers

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] Figure 1A is a block diagram illustrating a graphics system 100 according to an embodiment. In one embodiment, texture cache unit 110 is part of graphics processing unit (GPU) 106 . In one embodiment, the texture cache unit 110 includes a texture cache architecture, described below with respect to Figure 1B Describe it in more detail.

[0021] In one embodiment, GPU 106 may include graphics hardware and implement a graphics pipeline including, for example, one or more shader cores. External graphics memory 112 may be provided to store additional texture data. In one embodiment, central processing unit (CPU) 101 and associated system memory 102 may include computer program instructions for driver software 104 . The bus may be used to communicatively couple CPU 101 to GPU 106 , system memory 102 to CPU 100 , and GPU 106 to external graphics memory 112 .

[0022] Figure 1B An embodiment of the texture cache architecture 108 is illustrated in more detail. A level 0...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A texture cache architecture facilitates access of compressed texture data in non-power of two formats, such as the Adaptive Scalable Texture Compression (ASTC) codec. In one implementation, the texture cache architecture includes a controller, a first buffer, a second buffer, and a texture decompressor. A first buffer stores one or more blocks of compressed texel data fetched, in response to a first request, from a first texture cache, where the one or more blocks of compressed texel data including at least requested texel data. The second buffer stores decompressed one or more blocks of compressed texel data and provides the decompressed requested texel data as output to a second texture cache. The one or more blocks of compressed texel data stored by the first buffer includes second texel data in addition to the requested texel data.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application No. 62 / 303,889, filed March 4, 2016, the contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention generally relate to techniques for using texture caches in graphics processing units. Background technique [0004] In graphics systems, textures are usually stored in a texture cache in a compressed format. For example, a block compression format may compress the color and alpha of a 4x4 pixel block into 64 bits (64b; 8 bytes (8B)). After decompression, there are 2B red, green and blue (RGB) components, each of 5 bits, 6 bits, 5 bits respectively. Thus, this compression format achieves a compression factor of 4 (eg, for a 4x4 pixel block, 2B / pixel*16 pixels) / 8B=4). [0005] This compressed format achieves savings in memory requirements as well as the bandwidth required to move textures between ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F12/0842G06F12/0897G06T1/60
CPCG06F12/0842G06F12/0897G06T1/60
Inventor S.亚伯拉罕K.拉马尼徐雄权劝宅朴贞爱
Owner SAMSUNG ELECTRONICS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com