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Apparatus and method for cache memory connection of texture mapping

a cache memory and texture mapping technology, applied in the field of cache memory connection apparatus and method, can solve the problems of large area occupied by prior single cache memory, slow texture mapping speed, and large area occupied by cache memory 12

Inactive Publication Date: 2003-06-03
XGI TECHNOLOGY
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the texture mapping process needs to access a lot of texels in a DRAM.
If the bandwidth of the DRAM is inadequate, the speed of texture mapping will slow down.
A well-known method for improving the hit ratio is to increase the quantity of the cache memory 12, but this method will increase the area occupied and cost of the cache memory 12.
Therefore the cost and area occupied by the prior single cache memory is very large.
The prior art in dealing with multiple pixels or multiple textures accessed in one cycle is to use a cache memory 12 with a lot of data ports, and that is not economical enough.
As mentioned above, the current apparatus and method about cache memory connection for texture mapping do not meet the need by the market.

Method used

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Embodiment Construction

FIG. 2 is a schematic diagram of cache memories which implement a mapping method through a single pixel and single texture according to the first preferred embodiment of the present invention. The schematic diagram divides the prior single cache memory into four smaller cache memories with one fourth memory size of prior single cache memory and one fourth number of data ports of prior single cache memory, and the four smaller cache memories are named as a first cache memory 21, a second cache memory 22, a third cache memory 23 and a fourth memory 24. The input end is addresses 0 to 7, wherein address 0 is the address line of the first texel, by the same rule, address 7 is the address line of the eighth texel because one pixel is corresponding to eight texels at most in the major mapping methods of selecting the nearest point, bilinear filtering and trilinear filtering. There is a first multiplexer 25 between the third cache memory 23 and the input address end a second multiplexer 26...

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Abstract

The present invention discloses an apparatus and method for cache memory connection of texture mapping, applied in a computer graphic processing system by storing image texels in cache memories. The apparatus comprises a plurality of cache memories. An array of image texels are stored in a plurality of cache memories to reduce the area occupied by cache memories of the computer graphic processing system. Besides, the apparatus and method of the present invention can be applied in the well-known mapping methods: selecting the nearest point, bilinear filtering and trilinear filtering. A plurality of multiplexers are used to reorganize the plurality of cache memories so as to increase the utilization efficiency of the apparatus of the present invention.

Description

1. Field of the InventionThe present invention relates to an apparatus and method of cache memory connection stores image texels, and particularly to an apparatus and method for reducing area occupied and cost of cache memories by a special texture mapping process.2. Description of the Related ArtTexture mapping is important for a 3D computer graphic processing system because it riches the visual effect of a rendering process. However, the texture mapping process needs to access a lot of texels in a DRAM. If the bandwidth of the DRAM is inadequate, the speed of texture mapping will slow down.Nowadays in industries, a cache memory is used to resolve the problem of the bandwidth inadequacy when the DRAM is used. FIG. 1 is a structural diagram of a 3D computer graphic processing system, wherein a 3D graphic engine 11 is a kernel device for executing the rendering process, accesses a DRAM 15 through a DRAM controller 14 and accesses a cache memory 12 through a cache controller 13. Besid...

Claims

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Application Information

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IPC IPC(8): G06T11/40
CPCG06T11/40
Inventor LIAO, MING-HAOPAI, HUNG-TA
Owner XGI TECHNOLOGY
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