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Multi-core processor meeting SystemC grammar request and method for acquiring performing code

A multi-core processor and code execution technology, applied in the field of multi-core processors, can solve problems such as immature parallel languages ​​and achieve the effect of reducing the difficulty of development

Active Publication Date: 2008-06-11
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

From the perspective of computer science, the main reason is that parallel languages ​​such as OCAR, SISAL and PCN are not yet mature.

Method used

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  • Multi-core processor meeting SystemC grammar request and method for acquiring performing code
  • Multi-core processor meeting SystemC grammar request and method for acquiring performing code
  • Multi-core processor meeting SystemC grammar request and method for acquiring performing code

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] As shown in Figure 1, the multi-core processor that meets the SystemC syntax requirement of the present invention includes: a plurality of exchange units A14 connected to form an array for exchanging data, a plurality of processing units A13 for data processing and the exchange unit A14 Connection; also includes: a local resource unit A16 connected between adjacent processing units A13 for synchronization and data sharing between adjacent processing units, and at least one connected to the switching unit A14 for all processing units Global resource unit A17 for synchronization and data sharing.

[0051] As an implementable manner, in the multi-core processor shown in FIG. 1, the eight processing units P(0,0), P(0,1), P(0,2), P(1,0) , P(1,2), P(2,0), P(2,1) and P(2,2) communicate through the two-dimensional network formed by the switching unit A14, not all The components are all processors, of which A17 is a global resource unit. A16 is a local resource unit connected ...

Embodiment 2

[0085] The difference between this implementation and Example 1 is that: the local resource unit A16 includes a plurality of components that meet the syntax requirements of SystemC, and as an implementable manner, specifically includes: 1 instantaneous event (sc_event) unit, 1 memorable event queue (sc_event_queue), 1 mutex (sc_mutex) unit, 1 semaphore (sc_semaphore) unit, and 1 bidirectional input and output queue (sc_fifo); the global resource unit A17 includes a plurality of parts that meet the syntax requirements of SystemC, as An implementable manner specifically includes: 1 transient event (sc_event) unit, 1 memorable event queue (sc_event_queue), 1 mutex (sc_mutex) unit, 1 semaphore (sc_semaphore) unit, and 1 A bidirectional input and output queue (sc_fifo).

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Abstract

The invention discloses a polynuclear processor satisfying SystemC grammatical requirements and a method of acquiring the related execution codes. The polynuclear processor comprises: an array formed by connection of a plurality of switching units for switching data, a plurality of processing units for data processing connected with the switching units; a local resource unit connected between adjacent processing units for synchronizing and data sharing between adjacent processing units, as well as at least one global resource unit connected with the switching unit for synchronizing and data sharing between all the processing units. The method comprises: step S1, translating SystemC software model into codes which can be coded by an instruction set complier of the processing unit; step S2, mapping the process in the software model on the processing unit, and mapping grammatical elements in the SystemC respectively on the local resource unit and the global resource unit. The invention can obviously lower the developing difficulty of the embedded type system.

Description

technical field [0001] The invention relates to a multi-core processor, in particular to a multi-core processor meeting the syntax requirements of SystemC transaction processing level and a method for obtaining its execution code. Background technique [0002] In existing computer systems, the parallel execution of multiple threads is realized based on the operating system. The design method of executing multiple threads at the same time conforms to the basic way of thinking of human beings, and also conforms to the basic principle of parallel development and progress of the objective world. [0003] Before the emergence of multi-core processor technology, computer software systems were essentially serially executed. Before the emergence of multi-core processors, field programmable gate arrays (FPGAs) were the most widely used natural parallel large-scale integrated circuits by technicians. Humans have used FPGAs for many years, mainly for fast ASIC prototyping and cost-in...

Claims

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Application Information

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IPC IPC(8): G06F9/45
Inventor 陈曦范东睿张浩
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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